~ National ~ Semiconductor - Al Kossow's Bitsavers

15.0 Switching Characteristics (Continued)
DMA Control, Bus Arbitration
T4 n T2 T3 T4 n T2 T3 T4 n T2 T3 T4 n T2 T3 T4 n T2 T3
brqhl
BREQ
C
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w
CD
o
......
z
en
w
N
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CD
o
BACK
--''-------11---'1
ADSO -------+--~.:-.-I. r....-T--+-+-"\
bcctr
ADO-15 ---------------------t~~~-~-::-:-!-:-~-~-~-~-::-t__1
DATA
MWR.MRD ------------------------~.~.------~.~------____ .11
FIRST TRANSFER I FIRST TRANSFER I
- IF BACK SEEN ON -----r-- IF BACK NOT GIVEN -1
FIRST T1. ON FIRST n.
LAST TRANSFER
TL/F/8582-80
Symbol Parameter Min Max Units
brqhl Bus Clock to Bus Request High for Local DMA 43 ns
brqhr Bus Clock to Bus Request High for Remote DMA 38 ns
brql Bus Request Low from Bus Clock 50 ns
backs
Acknowledge Setup to Bus Clock
(Note 1)
bccte Bus Clock to Control Enable 60 ns
bcctr
Bus Clock to Control Release
(Notes 2,3)
2
ns
70 ns
Note 1: BACK must be setup before T1 after BREQ is asserted. Missed setup will slip the beginning of the OMA by four bus clocks. The Bus Latency will influence
the allowable FIFO threshold and transfer mode (empty Ifill vs exact burst transfer).
Note 2: During remote DMA transfers only, a single bus transfer is performed. During local DMA operations burst mode transfers are performed.
Note 3: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns enabling other devices to drive these lines with
no contention.
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