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-----------------------------------------------------------------------,c "a 6.0 Instruction Set Reference (Continued) XOR Exclusive OR Immediate Syntax XOR n, rsd -immediate, limited register Affected Flags N,Z Description Logically exclusive ORs the immediate value n to the register rsd and places the result back into the register rsd. Note that only the active registers RO-R15 may be specified for rsd. The value of n is 8 bits wide. Example Encode/decode a data byte in register 20. XOR code-pattern, R20 ;encode/decode Instruction Format 1 0 11 1 1 1 0 I . Opcode . 15 11 T-states 2 Bus Timing Figure 7 Operation rsd XOR n - rsd n rsd 3 0 XORA Exclusive OR with Accumulator Syntax XORA Rs, Rd XORA Rs, [mlr] -register, register -register, indexed Affected Flags N,Z Description Logically exclusive ORs the source register Rs to the active accumulator and places the result into the destination specified. The destination may be either a register, Rd, or data memory via an index register mode, [mlr]. Note that register bank selection determines which accumulator is active. Example Decode the data byte just received and place it into data memory. This example assumes that the accumulator contains the "key" and that the index register IY points to the location where the information should be stored. EXX 1,1 ;select alternate banks XORA Instruction Format XORA Rs, Rd RTR, [IY + ] ;decode received byte and ; save it 15 9 XORA Rs, [Mlr] 1 Rd 15 8 6 4 T-states XORA Rs, Rd -2 XORA Rs, [mlr] -3 00 - post-decrement 01 - no change 10 - post Increment 11 - pre-Increment Bus Timing XORA Rs, Rd -Figure 7 XORA Rs, [mlr] -Figure 12 Operation XORA Rs, Rd Rs XOR accumulator - XORA Rs, [mlr] Rs XOR accumulator - Rd data memory 4 1 1 Rs i i R. ~ 00 -IW 01 - IX 10 - IY 11 - IZ o o TL/F/9336-16 co W ... ; 2-123
6.0 Instruction Set Reference (Continued) Instruction TABLE XXIII. Instruction Verse T-states, Affected Flags, and Bus Timing T-states Affected Timing Affected Timing Instruction T-states Flags Figure Flags Figure ADCA Rs, Rd 2 N,Z,C,V 7 MOVE Rs, Rd 2 7 ADCA Rs, [mlrl 3 N,Z,C,V 12 MOVE Rs, [mlr] 3 12 ADD n, rsd 2 N,Z,C,V 7 MOVE Rs, [lr + <strong>Al</strong> 3 12 ADDA RS,Rd 2 N,Z,C,V 7 MOVE rs, [lZ + nl 3 12 ADDA Rs, [mlrl 3 N,Z,C,V 12 MOVE [mlr],Rd 3 11 AND n, rsd 2 N,Z 7 MOVE [lr + <strong>Al</strong>,Rd 3 11 ANDA RS,Rd 2 N,Z 7 MOVE [IZ + nl, rd 3 11 ANDA Rs, [mlrl 3 N,Z 12 OR n, rsd 2 N,Z 7 BIT rs, n 2 N,Z 7 ORA Rs, Rd 2 N,Z 7 CALL n 3 8 ORA Rs, [mlrl 3 N,Z 12 CMP rs, n 2 N,Z,C,V 7 Rcc (g (,rf}} 2 false 7 3 true N,Z,C,V* CPL Rsd 2 N,Z 7 8 RET (g (,rfll 2 N,Z,C,V' EXX ba, bb (,g} 2 7 7 Jee n 2 false 7 RETF f, s (,(g} (,rfll 2 false 7 3 true 8 3 true N,Z,C,V* 8 JMP f, s, n 2 false 7 ROT Rsd, b 2 N,Z,C 7 3 true 8 SBCA Rs, Rd 2 N,Z,C,V 7 JMP n 3 8 SBCA Rs, [mlrl 3 N,Z,C,V 12 JMP Rs 4 10 SHL Rsd, b 2 N,Z,C 7 JRMK RS,b,m 4 10 SHR Rsd, b 2 N,Z,C 7 LCALL nn (2+2) 9 SUB n, rsd 2 N,Z,C,V 7 LCALL Rs, p, s, nn (2+2) 9 SUBA RS,Rd 2 N,Z,C,V 7 LJMP nn (2+2) 9 SUBA Rs, [mlrl 3 N,Z,C,V 12 LJMP [lrl 2 7 TRAP v (,g'} 2 7 LJMP Rs,p,s,nn (2+2) 9 XOR n, rsd 2 N,Z 7 MOVE n, rd 2 7 XORA Rs, Rd 2 N,Z 7 MOVE n, [lrl 3 12 XORA Rs, [mlrl 3 N,Z 12 'If rf = 1 then N, Z, C, and V are affected. 2-124
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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13.0 Bus Arbitration and Timing The
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15.0 Switching Characteristics AC S
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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~~L ~------------------------------
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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N r--------------------------------
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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C") "Ot "Ot N C") en ...... z C") "
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) r--------------------------------
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Absolute Maximum Ratings (Note 1) I
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(W) r------------------------------
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M r--------------------------------
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MUX~ __________________ The BIPLAN
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U) ,-------------------------------
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~r---------------------------------
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~ .--------------------------------
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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Page 267 and 268: 6.0 Instruction Set Reference (Cont
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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m . r------------------------------
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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m r--------------------------------
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~ &I) o N m Z ::::: o &I) 'Of' o co
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~ Lt) o N co U) Z ::::: o Lt) '
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4.0 Timing Waveforms (Continued) Re
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6.0 Pin Descriptions (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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fj ::z:: ~ :::IE :::IE ~ ,---------
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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.... ~ ~ U) r----------------------
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..... U) z • U) r----------------
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~ .... ,---------------------------
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.,... U) Z 3020 LPRINT USING" 1111
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. II) or- II) Z
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,.. i ~~---------------------------
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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• I .----------------------------
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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t-------------I:..':::~"':I'-------
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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~ National ~ Semiconductor
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