~ National ~ Semiconductor - Al Kossow's Bitsavers

13.0 Bus Arbitration and Timing (Continued)
When in 32-bit mode four additional BSCK cycles are required
per burst. The first bus cycle (Tl' - T 4') of each burst
is used to output the upper 16-bit addresses. This 16-bit
address is programmed in RSARO and RSARl and points to
a 64k page of system memory. All transmitted or received
packets are constrained to reside within this 64k page.
FIFO BURST CONTROL
All Local DMA transfers are burst transfers, once the DMA
requests the bus and the bus is acknowledged, the DMA will
BREO
---.I
transfer an exact burst of bytes programmed in the Data
Configuration Register (DCR) then relinquish the bus. If
there are remaining bytes in the FIFO the next burst will not
be initiated until the FIFO threshold is exceeded. If desired
the DMA can empty/fill the FIFO when it acquires the bus. If
BACK is removed during the transfer, the burst transfer will
be aborted. (DROPPING BACK DURING A DMA CYCLE IS
NOT RECOMMENDED.)
,'-----
BACK
--~I ~
C
"tI
co
Co)
CD
o
......
z
(J)
Co)
N
.j:Oo
CD
o
AOO-15 ~ ................ ~.
I~NE'BURST ~I
where N = 1, 2, 4, or 6 Words or N = 2, 4, 8, or 12 Bytes when in byte mode
TLlF/8582-69
INTERLEAVED LOCAL OPERATION
If a remote DMA transfer is initiated or in progress when a
packet is being received or transmitted, the Remote DMA
transfer will be interrupted for higher priority Local DMA
BREO ---.I '~___
I
BACK
transfers. When the Local DMA transfer is completed the
Remote DMA will rearbitrate for the bus and continue its
transfers. This is illustrated below:
'..._--
ADO-15
TL/F/8582-70
Note that if the FIFO requires service while a remote DMA is
in progress, BREQ is not dropped and the Local DMA burst
is appended to the Remote Transfer. When switching from
a local transfer to a remote transfer, however, BREQ is
dropped and raised again. This allows the CPU or other
devices to fairly contend for the bus.
REMOTE DMA-BIDIRECTIONAL PORT CONTROL
The Remote DMA transfers data between the local buffer
memory and a bidirectional port (memory to I/O transfer).
This transfer is arbited on a byte by byte basis versus the
burst transfer used for Local DMA transfers. This bidirectional
port is also read/written by the host. All transfers
through this port are asynchronous. At anyone time transfers
are limited to one direction, either from the port to local
buffer memory (Remote Write) or from local buffer memory
to the port (Remote Read).
Bus Handshake Signals for Remote DMA Transfers
BIDIRECTIONAL PORT
NIC SIGNALS
DMA SIGNALS
~
OEA
8/16
CKA
DATA 4
7 '- ~
PWR
~ CKB
• OEB
RACK
Y
4
7 (
8/16
~
lOW
DATA
lORD
PRO ~.-----------+~ ORO
TLlF/8582-71
1-33