~ National ~ Semiconductor - Al Kossow's Bitsavers

7.0 CPU Registers (Continued)
BIT DEFINITION TABLE (Continued)
TRANSCEIVER (Continued)
Table includes control and status bits only. It does not include definitions of bit fields provided for the formatting (de-formatting)
data frames. For further information see the Transceiver Section. (Continued)
Bit Name Location Reset State Function
Transceiver TCS1,0 Transceiver Clock DCR [6,5] 10 Selects transceiver clock, TCLK, source.
Control Select TCS1,O TCLK
(Continued)
00 OCLK
01 OCLK/2
10 OCLK/4
11 X-TCLK
OCLK is the frequency of the on-chip oscillator, or the
externally applied clock on input X1. X-TCLK is the external
transceiver clock input.
TRES Transceiver RESet TMR [7] 0 Resets transceiver when high. Transceiver can also be reset
by RESET, without affecting [TRES].
Transmitter ATA Advance Transmitter TCR [4] 0 When high, TX-ACT is advanced one half bit time so that the
Control Active transmitter can generate 5.5 line quiesce pulses.
AT7-3 Auxilliary ATR [7-3] XXXXX In 5250 modes. Controls the time TX-ACT is held after the last
Transceiver Control
fill bit.
AT7-3 TX-ACT Hold Time (ILs)
00000 0
00001 0.5
00010 1
!- !-
1 1 1 1 1 15.5
FB7-0 Fill Bits FBR [7-0] XXXXXXXX The value in this register contains the 1 's complement of the
number of additional 5250 fill bits selected.
OWP Odd Word Parity TCR [3] 0 Controls transmitter word parity.
OWP
Word Parity
0 Even
1 Odd
TF10-8 Transmit FIFO TCR [2-0] 000 [OWP], [TF10-8] and [RTF7 -0] are pushed onto the
transmit FIFO on moves to {RTR I.
TIN Transmitter INvert TMR [3] 0 When high, the transmitter serial data outputs are inverted.
Receiver AT7-0 Auxilliary ATR [7-0] XXXXXXXX In 5250 modes, [AT2-0] contains the station address. In 8-bit
Control Transceiver Control modes, [AT7-0] contains the station address.
RF10-8 Receiver FIFO TSR [2-0] XXX Reflects the state of the most significant 3 bits in the top
location of the receive FIFO.
RIN Receiver INvert TMR (4) 0 When high, the receiver serial data is inverted.
RLQ Receive Line TCR (7) 1 Selects number of line quiesce bits the receiver requires
Quiesce
before it will indicate receipt of a valid start sequence.
RLQ Number of Line Quiesce Pulses
0 2
1 3
RPEN RePeat ENable TMR (5) 0 When high, the receiver can be active at the same time as the
transmitter.
SEC Select Error Codes TCR [6] 0 When high {ECR I is switched into {RTR) location.
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