~ National ~ Semiconductor - Al Kossow's Bitsavers

8.0 Remote Interface and Arbitration System (Continued)
interaction. In addition, two bits allow the BCP CPU to keep
track of remote accesses. These bits are the Remote Write
bit [RW] and the Remote Read bit [RR], and are located in
(CCR[6-5]l. Each bit goes high when its respective remote
access to DMEM reaches its Termination Phase. Once one
of these bits has been set, it will remain high until a "1" is
written to that bit to reset it low.
DETAILED TIMING
In this section, the operation of the Remote Arbitration State
Machine (RASM), is described in detail. Discussed, among
other things, are the sequence of events in a remote access,
arbitration of the data buses, timing of external signals,
when inputs are sampled, and when wait states are
added. Each of the five Interface Modes is described in
functional state machine form. Although each interface
mode is broken out in a separate flow chart, they are all part
of a single state machine (RASM). Thus the first state in
each flow chart is actually the same state.
The functional state machine form is similar to a flow chart,
except that transitions to a new state (states are denoted as
rectangular boxes) can only occur on the rising edge of the
internal CPU clock (CPU-ClK). CPU-ClK is high during the
first half of its cycle. A state box can specify several actions,
and each action is separated by a horizontal line. A signal
name listed in a state box indicates that that pin will be
asserted high when RASM has entered that state. Signals
not listed are assumed low.
Note: This sometimes necessitates using the inversion of the external pin
name). This same rule applies to the A and AD buses. By default,
these buses are active. The A bus will have the upper byte of the last
used data address.
The AD bus will display (RICl. When one of these buses
appears in a state box, the condition specified will be in
effect only during that state. Decision blocks are shown as
diamonds and their meaning is the same as in a flow chart.
The hexagon box is used to denote a conditional state-not
synchronous with the clock. When the path following a decision
block encounters a conditional state, the action specified
inside the hexagon box is executed immediately.
Also provided is a memory arbitration example in the form of
a timing diagram for each of the five modes. These examples
show back to back local accesses punctuated by a
remote access. Both the state of RASM and the Timing
Control Unit are listed for every clock at the top of each
timing diagram. The RASM states listed correspond to the
flow charts. The Timing Control Unit states are described in
the CPU Timing portion of the data sheet.
Buffered Read
The unique feature of this mode is the extension of the read
until REM-RD is deasserted. The complete flow chart for the
Buffered Read mode is shown in Figure 25. Until a Remote
Read is initiated (RAE*REM-RD true), the state machine
(RASM) loops in state RSA. If [lOR] is set high, RASM will
loop in RSA indefinitely. If the BCP CPU needs to access
Data Memory at this time (and lOCK is high), it can still do
so. A local access is requested by the Timing Control Unit
asserting the local Bus Request (lCl-BREQ) signal. A local
bus grant will be given by RASM if the buses are not being
used (as is the case in RSA).
XACK is taken low as soon as RAE*REM-RD is true, regardless
of an ongoing local access. RASM will move into
RSs on the next clock after RAE*REM-RD is true and there
is no local bus request. No further local bus requests will be
granted until the remote access is complete and RASM returns
to RSA.
On the next CPU-ClK, RASM enters RSe and lCl is taken
high along with XACK. The wait state counters, ilw and iow,
are loaded in this state from [lW1-0] and [DW2-0], respectively,
in (DCR l. The A bus (and AD if the access is to Data
Memory) now goes into TRI-STATE and the Access Phase
begins.
The state machine can move into one of several states depending
on the state of CMD and [MS1-0] on the next
clock. XACK and lCl are still asserted in all the possible
next states. If CMD is high, the access is to (RIC l and the
next state will be RS01. Since the default state of AD is
(RIC l. it will not transition in this state.
The five other next states all have CMD low and depend on
the Memory Select bits. If [MS1-0] is 10 or 11 the state
machine will enter either RS02 or RS03 and the low or high
bytes of the Program Counter, respectively, will be read.
[MS1-0] = 00 designates a Data Memory access and
moves RASM into RS04. READ will be asserted in this state
and A and AD continue to be at TRI-STATE. This allows the
Remote Processor to drive the Data Memory address for
the read. Since DMEM is subject to wait states, RSo4 is
looped upon until all the wait states have been inserted.
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