~ National ~ Semiconductor - Al Kossow's Bitsavers

15.0 Switching Characteristics AC Specs DP8390C Note: All Timing is Preliminary
RAO-3~~
Aosa
~rss
aswl
rsh
Register Read (Latched Using ADSO)
---------------------------------------
rsrsl __
cs \.\\'\ /////
C
"tI
QC)
Co)
CD
C
o
......
z
(J)
Co)
N
"'"
CD
C
o
_rackl
--------~I
ACK
I---ackdv
..... trackh
1
I:::jrdZ
ADa-7--------------------------------------1::::::§OO~-~7::::::}_-----
TL/F/8582-76
Symbol
rss
rsh
aswi
ackdv
rdz
rackl
rackh
rsrsl
Parameter
Register Select Setup to ADSO Low
Register Select Hold from ADSO Low
Address Strobe Width In
Acknowledge Low to Data Valid
Read Strobe to Data TRI-STATE
Read Strobe to ACK Low (Notes 1 , 3)
Read Strobe to ACK High
Register Select to Slave Read Low,
Latched RSO-3 (Note 2)
Min
Max
10
13
15
55
15 70
n*bcyc + 30
30
10
Units
ns
ns
ns
ns
ns
ns
ns
Note 1: ACR is not generated until CS and SAD are low and the NIC has synchronized to the register access. The NIC will insert an integral number of Bus Clock
cycles until it is synchronized. In Dual Bus systems additional cycles will be used for a local or remote DMA to complete. Wait states must be issued to the CPU until
7iCK is asserted low.
Note 2: CS may be asserted before or after SRD. If CS is asserted after SRD, rackl is referenced from falling edge of CS. CS can be de-asserted concurrently with
SliD or after SRD is de-asserted.
Note 3: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns, enabling other devices to drive these lines with
no contention.
ns
1-37