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3.0 AC Electrical Characteristics TA = O"Cto +70'C, Vcc = +5V ±5% Symbol Parameter Conditions Min Max Units tAOS Address Strobe Width 60 ns tAH Address Hold Time 0 ns tAR RD, RD Delay from Address (Note 1) 30 ns tAS Address Setup Time 60 ns tAW WR, WR Delay from Address (Note 1) 30 ns tCH Chip Select Hold Time 0 ns tcs Chip Select Setup Time 60 ns tcSR RD, RD Delay from Chip Select (Note 1) 30 ns tcsw WR, WR Delay from Select (Note 1) 30 ns tOH Data Hold Time 30 ns tos Data Setup Time 30 ns tHZ RD, RD to Floating Data Delay @100pFloading(Note3) 0 100 ns tMR Master Reset Pulse Width 5 ,...s tRA Address Hold Time from RD, RD (Note 1) 20 ns tRC Read Cycle Delay 125 ns tRCS Chip Select Hold Time from RD, RD (Note 1) 20 ns tRO RD, RD Strobe Width 125 ns tROD RD, RD to Driver Enable/Disable @100 pF loading (Note 3) 60 ns tRVO Delay from RD, RD to Data @100pFloading 125 ns tWA Address Hold Time from WR, WR (Note 1) 20 ns twc Write Cycle Delay 150 ns twcs Chip Select Hold Time from (Note 1) 20 ns WR,WR tWR WR, WR Strobe Width 100 ns tXH Duration of Clock High Pulse External Clock (8.0 MHz Max.) 55 ns tXL Duration of Clock Low Pulse External Clock (8.0 MHz Max.) 55 ns RC Read Cycle = tAR + tRO + tRC (Note 4) 280 ns WC Write Cycle = tAW + tWR + twc 280 ns Baud Generator N Baud Divisor 1 216-1 tBHO Baud Output Positive Edge Delay 100 pF Load 175 ns tBLO Baud Output Negative Edge Delay 100 pF Load 175 ns tHW Baud Output Up Time fx = 8.0 MHz, + 2, 100 pF Load 75 ns tLW Baud Output Down Time fx = 8.0 MHz, + 2, 100 pF Load 100 ns Receiver tRINT Delay from RD, RD (RD RBR/or RD LSR) 100 pF Load 1 ,...s to Reset Interrupt tsco Delay from RCLK to Sample Time 2 ,...s tslNT RCLK Delay from Stop to Set Interrupt (Note 2) 1 Cycles Note 1: Applicable only when ADS is tied low. Note 2: In the FIFO mode (FCRO -1) the trigger level interrupts. the receiver dais available indication. the active RXRDY indication and the overrun error indication will be delayed 3 RCLKs. Sistus indicators (PE. FE. BI) will be delayed 3 RCLKs after the first byte has been received. For subsequently received bytes these indicators will ba updated immediately after RDRBR goes inactive. Timeout interrupt is delayed 8 RCLKs. Note 3: Charge and discharge time is determined by VOlo VOH and the external loading. Note 4: In FIFO mode RC - 425 ns (minimum) between reeds of the receiver FIFO and the slstus registers (interrupt idenmication register or line status register). z U) ..... 0) CII CII ~ 4-39
3.0 AC Electrical Characteristics (Continued) Symbol I Parameter I Conditions I Min I Max I Units Transmitter tHR Delay from WR, WR (WR THR) 100 pF Load 175 ns to Reset Interrupt tlR Delay from RD, RD (RD IIR) to Reset 100 pF Load 250 ns Interrupt (THRE) tlRS Delay from InitiallNTR Reset to Transmit 8 24 BAUDOUT Start Cycles tSI Delay from Initial Write to Interrupt (Note 1) 16 24 BAUDOUT Cycles tSTI Delay from Stop to Interrupt (THRE) (Note 1) 8 8 BAUDOUT Cycles tSXA Delay from Start to TXRDY active 100 pF Load 8 BAUDOUT Cycles tWXI Delay from Write to TXRDY inactive 100 pF Load 195 ns Modem Control tMOO Delay from WR, WR (WR MCR) to 100 pF Load 200 ns Output tRIM Delay to Reset Interrupt from RD, RD 100 pF Load 250 ns (RDMSR) tSIM Delay to Set Interrupt from MODEM Input 100 pF Load 250 ns Note 1: This delay will be lengthened by 1 character time, minus the last stop bit time if the transmitter interrupt delay circuit is active. (See FIFO Interrupt Mode Operation). 4.0 Timing Waveforms (<strong>Al</strong>l timings are referenced to valid 0 and valid 1) External Clock Input (8.0 MHz Max.) AC Test Points 2.4V tXH 2.0V Z.4V i NOTE I Z.OV NOTEZ XIN 0.8V O.4V 0.8V O.4V TLlC/8652-3 I~I TL/C/8652-2 Note 1: The 2.4V and O.4V levels are the voltages that the inputs are driven to during AC testing. Note 2: The 2.0V and O.BV levels are the voltages at which the timing tests are made. XIN BAUDOUT Timing I' N I 'IHD...j I- 'ILD--! I- -I I-'HW lAUD OUT LJ'ULnflJ1 (+11 mJlflIlJT (+21 iAii1lfOT (+31 --l I+-'IHO -.j i--'ILO -.j !--'ILO --I I-'ILO ---II-'IHO -I ~'LW 'LW.j j.'HW..J ~ j..-'IHO j.'HW+-'LW---! I' JlJ1Jl.J1- ·ltw"'(N-2I XINCYCLES IAUifDijf (+1,1>31 ~' I r~ I· .ltLW'" 2 XIN CYCLES TLlC/B652-4 4·40
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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13.0 Bus Arbitration and Timing The
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15.0 Switching Characteristics AC S
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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~~L ~------------------------------
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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C") "Ot "Ot N C") en ...... z C") "
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Absolute Maximum Ratings (Note 1) I
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(W) r------------------------------
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M r--------------------------------
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MUX~ __________________ The BIPLAN
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U) ,-------------------------------
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~r---------------------------------
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~ .--------------------------------
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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~ ~ 4.0 Electrical Specifications (
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c( '
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~L ______________ ___ ~ ~ 4.0 Elect
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ C') 6.0 Instruction Set Reference
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! 6.0 Instruction Set Reference (Co
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~ ~ 6.0 Instruction Set Reference (
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== ~ 6.0 Instruction Set Reference
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ ~ HASM state TCU state eLK-OUT RE
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~I tn tn ...._,__'RS A RS, RSC IMEM
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ ~ I\~"'''' I 'ow = "[OW2-0) , RS
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~ 8l HASM stat. TCU stat. CU- C» b
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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Page 396 and 397: NSC Solutions: Systems Level Basic
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Page 400 and 401: ~National ~ Semiconductor PRELIMINA
Page 402 and 403: ISDN DEFINITIONS "B" Channel, or DS
Page 404: ~ '" TE2 UP TO 8 TERMINALS -
Page 407 and 408: Section 4 Contents INS8250/INS8250-
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Page 411 and 412: 3.0 AC Electrical Characteristics T
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Page 415 and 416: 5.0 Block Diagram INTERNAL DATA IUS
Page 417 and 418: 6.0 Pin Descriptions (Continued) In
Page 419 and 420: 8.0 Registers (Continued) and 1, on
Page 421 and 422: 8.0 Registers (Continued) 8.5 INTER
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Page 425 and 426: ~ &I) o N m Z ::::: o &I) 'Of' o co
Page 427 and 428: ~ Lt) o N co U) Z ::::: o Lt) '
Page 430 and 431: 4.0 Timing Waveforms (Continued) Re
Page 432 and 433: 6.0 Pin Descriptions (Continued) Re
Page 434 and 435: 8.0 Registers The system programmer
Page 436 and 437: 8.0 Registers (Continued) 8.3 PROGR
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Page 440 and 441: 9.0 Typical Applications (Continued
Page 442 and 443: Table of Contents 1.0 ABSOLUTE MAXI
Page 446 and 447: 4.0 Timing Waveforms (Continued) Wr
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Page 450 and 451: 5.0 Block Diagram AO A, A2 CSD CSI
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Page 460 and 461: '" .j>. 01 PHil This shows the basi
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Page 464 and 465: 3. The Rx FIFO will hold 16 bytes r
Page 466 and 467: NS16550A E-J r-o ..... IRQ4 ICU CPU
Page 468 and 469: TITLE 550APP.ASM - NS16550A INITIAL
Page 470 and 471: 3.0 Board to Board Communications w
Page 472 and 473: DIAPPS.ASM Flow Chart l> z • ~ CO
Page 474 and 475: » z I "" CD RDAI: DISABLE IRTS, SE
Page 476 and 477: COMPARE: SET UP COMPARE BUffER POIN
Page 478 and 479: .set iCu imsk,lO *aO • set icu -c
Page 480 and 481: holdloop: nop # br hold loop # # #*
Page 482 and 483: # msint: save [rO,rl,r2,r3] # movd
Page 484 and 485: #3/30/B7••••• D2APPS.ASM
Page 486 and 487: # #*************************** 1655
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Page 490 and 491: A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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fj ::z:: ~ :::IE :::IE ~ ,---------
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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.... ~ ~ U) r----------------------
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..... U) z • U) r----------------
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~ .... ,---------------------------
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.,... U) Z 3020 LPRINT USING" 1111
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. II) or- II) Z
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,.. i ~~---------------------------
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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• I .----------------------------
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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t-------------I:..':::~"':I'-------
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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~ National ~ Semiconductor
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