Une Boite `a Outils Pour la Preuve Formelle de Syst`emes Séquentiels
Une Boite `a Outils Pour la Preuve Formelle de Syst`emes Séquentiels
Une Boite `a Outils Pour la Preuve Formelle de Syst`emes Séquentiels
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
144 BIBLIOGRAPHIE<br />
[14] G. Berry, “A Hardware Implementation of ESTEREL”, in Proc. of 1991 International<br />
Workshop on Formal Methods in VLSI Design, Miami FL, USA, janvier 1991.<br />
[15] G. Berry, “ESTEREL on Hardware”, in Proc. of The Royal Society Discussion Meeting<br />
on Mechanized Reasoning abd Hardware Design, London, UK, octobre 1991.<br />
[16] G. Berry et all., “The ESTEREL Language”, in IEEE Special Issue on Synchronous<br />
Languages, septembre 1992.<br />
[17] C. Berthet, O. Cou<strong>de</strong>rt, J. C. Madre, “New I<strong>de</strong>as on Symbolic Manipu<strong>la</strong>tions of<br />
Finite State Machines”, in Proc. of ICCD’90, Cambridge MA, USA, septembre 1990.<br />
[18] J. P. Billon, “Perfect Normal Forms for Discrete Functions”, BULL Research Report<br />
N o 87019, juin 1987.<br />
[19] J. P. Billon, “Symbolic Execution of Discrete Programs”, BULL Research Report<br />
N o 87039, Septembre 1987.<br />
[20] D. Borrione, J. L. Paillet, L. Pierre, H. Col<strong>la</strong>vizza, “Modélisation Fonctionnelle et<br />
<strong>Preuve</strong> <strong>de</strong> Circuits Digitaux”, TSI, Vol. 8, N o 6, pp. 523–544, 1989.<br />
[21] S. Bose, A. Fisher, “Automatic Verification of Synchronous Circuits Using Symbolic<br />
Logic Simu<strong>la</strong>tion and Temporal Logic”, in Formal VLSI Correctness Verification,<br />
L.J.M. C<strong>la</strong>esen Editor, North-Hol<strong>la</strong>nd, pp. 151–158, novembre 1989.<br />
[22] A. Bouajjani, J. C. Fernan<strong>de</strong>z, N. Halbwachs, “Verification of Safety Properties”,<br />
avril 1990.<br />
[23] A. Bouajjani, J. C. Fernan<strong>de</strong>z, N. Halbwachs, “Minimal Mo<strong>de</strong>l Generation”, in<br />
Computer-Ai<strong>de</strong>d Verification’90, E. M. C<strong>la</strong>rke and R. P Kurshan Editors, DIMACS<br />
Series, pp. 85–91, juin 1990.<br />
[24] A. Bou<strong>de</strong>t, J. P. Jouannaud, “Unification in Boolean Rings and Abelian Groups”,<br />
special issue of JSC, mai 1988.<br />
[25] R. K. Brayton, G. D. Hachtel, C. T. McMullen, A. L. Sangiovanni-Vincentelli, Logic<br />
Minimization Algorithms for VLSI Synthesis, Kluwer Aca<strong>de</strong>mic Publishers, 1984.<br />
[26] F. M. Brown, Boolean Reasoning, Kluwer Aca<strong>de</strong>mic Publishers, 1990.<br />
[27] R.E.Bryant,“Graph-BasedAlgorithmsforBooleanFunctionsManipu<strong>la</strong>tion”,IEEE<br />
Transactions on Computers, Vol C35, N 0 8, pp. 677–692, août 1986.<br />
[28] R. E. Bryant, “On the Complexity of VLSI Implementations and Graph Representations<br />
of Boolean Functions with Application to Integer Multiplication”, Carnegie<br />
Mellon University Research Report, septembre 1988.<br />
[29] S. Burch, E. M. C<strong>la</strong>rke, K. L. McMil<strong>la</strong>n, “Symbolic Mo<strong>de</strong>l Checking: 10 20 States<br />
and Beyond”, in Proc. of LICS, 1990.<br />
[30] S. Burch, E. M. C<strong>la</strong>rke, K. L. McMil<strong>la</strong>n, “Sequential Circuit Verification Using<br />
Symbolic Mo<strong>de</strong>l Checking”, in Proc. of 27th DAC, Or<strong>la</strong>ndo FL, USA, juillet 1990.