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Une Boite `a Outils Pour la Preuve Formelle de Syst`emes Séquentiels

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150 BIBLIOGRAPHIE<br />

[108] D. E. Ross, K. M. Butler, R. Kapur, M. R. Mercer, “Fast Functional Evaluation<br />

of Candidate OBDD Variable Or<strong>de</strong>rings”, in Proc. of 2nd EDAC, pp. 4–10, février<br />

1991.<br />

[109] J. S. Savage, The Complexity of Computing, Wiley-Interscience Publication, 1976.<br />

[110] H. Savoj, R. K. Brayton, H. Touati, “Extracting Local Don’t Cares for Network<br />

Optimization”, in Proc. of ICCAD’91, Santa C<strong>la</strong>ra CA, USA, novembre 1991.<br />

[111] D. A. Schmitt, A Methodology for Language Development, Allyn Bacon Inc., 1986.<br />

[112] H. Simonis, M. Dincbas, “Using Logic Programming for Fault Diagnosis in Digital<br />

Circuits”, ECRC Technical Report TR-LP-18, 1986.<br />

[113] H. Simonis, M. Dincbas, “Using an Exten<strong>de</strong>d Prolog for Digital Circuit Design”,<br />

ECRC Technical Report TR-LP-22, 1987.<br />

[114] V. Stavridou, H. Barringer and D. A. Edwards, “Formal Specification and Verification<br />

of Hardware - A Comparative Case Study”, in Proc. of the 25th DAC, Anaheim<br />

CA, USA, juillet 1988.<br />

[115] J. M. Steyaert, P. F<strong>la</strong>jolet, “Patterns and Pattern-Matching in Trees: An Analysis”,<br />

Information and Control, Vol 58, Nos 1–3, pp 19–58, Aca<strong>de</strong>mic Press, 1983.<br />

[116] R. S. Stoll, Set Theory and Logic, Dover Publications Inc., 1986.<br />

[117] M. Stone, “The Theory of Representations for Boolean Algebra”, Transactions AMS<br />

Vol. 40, pp. 37–111, 1936.<br />

[118] K. J. Supowit, S. J. Friedman, “A new Method for Verifying Sequential Circuits”,<br />

in Proc. of the 23rd DAC, 1986.<br />

[119] E. Ti<strong>de</strong>n, “Symbolic Verification of Switch-Level Circuits using a Prolog Enhanced<br />

with Unification in Finite Algebra”, in The Fusion of Hardware Design And Verification,<br />

North Hol<strong>la</strong>nd, 1988.<br />

[120] H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, A. Sangiovanni-Vincentelli, “Implicit<br />

State Enumeration of Finite State Machines using BDD’s”, in Proc. of ICCAD’90,<br />

Santa C<strong>la</strong>ra CA, USA, novembre 1990.<br />

[121] F. Van Aelten, J. Allen, S. Devadas, “Verification of Re<strong>la</strong>tions between Synchronous<br />

Machines”, in Proc. of ICCAD’91, Santa C<strong>la</strong>ra CA, USA, novembre 1991.<br />

[122] J. S. Vitter, P. F<strong>la</strong>jolet, “Average-Case Analysis of Algorithms and Data Stuctures”,<br />

Algorithms and Complexity, Handbook of Theorical Computer Science, Vol<br />

A, Chapter 9, pp. 433–524, Elsevier Science, 1990.<br />

[123] F. V<strong>la</strong>ch, “A Note on the INSTEP Tautology Checker and the IFIP and ISCAS<br />

Benchmarks”, in Formal VLSI Correctness Verification, L.J.M. C<strong>la</strong>esen Editor,<br />

North-Hol<strong>la</strong>nd, pp. 89–93, novembre 1989.

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