Une Boite `a Outils Pour la Preuve Formelle de Syst`emes Séquentiels
Une Boite `a Outils Pour la Preuve Formelle de Syst`emes Séquentiels
Une Boite `a Outils Pour la Preuve Formelle de Syst`emes Séquentiels
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148 BIBLIOGRAPHIE<br />
[78] J.Hsiang,“RewriteMethodsforTheoremProvinginFirstOr<strong>de</strong>rTheorywithEquality”,<br />
Journal of Symbolic Computation N o 3, pp. 133–151, 1987.<br />
[79] W. A. Hunt, “FM8501: A Verified Microprocessor”, in Proc. of the IFIP WG 10.2<br />
Workshop: From HDL Descriptions to Guaranteed Correct Circuit Designs, North<br />
Hol<strong>la</strong>nd Publishing, 1986.<br />
[80] S.H.Hwang, A.R.Newton, “AnefficientDesignCorrectnessCheckerofFiniteState<br />
Machines”, in Proc. of ICCAD’87, Santa C<strong>la</strong>ra, USA, novembre 1987.<br />
[81] S. W. Jeong, B. Plessier, G. D. Hachtel, F. Somenzi, “Variable Or<strong>de</strong>ring for FSM<br />
Traversal”, in Proc. of the MCNC Workshop, North Carolina, USA, mai 1991.<br />
[82] S. C. Kleene, Mathematical Logic, John Wiley and Sons, NY, 1967<br />
[83] S. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, New York, 1978.<br />
[84] R. P. Kurshan, “Analysis of discrete Event Coordination”, in Lecture Notes in Computer<br />
Science, Springer-Ver<strong>la</strong>g, pp. 414–453, 1990.<br />
[85] B. Lin, H. J. Touati, A. R. Newton, “Don’t Care Minimization of Multi-Level Sequential<br />
Logic Networks”, in Proc. of ICCAD’90, Santa-C<strong>la</strong>ra CA, USA, novembre<br />
1990.<br />
[86] B. Lin, “Efficient Symbolic Manipu<strong>la</strong>tion of Equivalence Re<strong>la</strong>tions and C<strong>la</strong>sses”, in<br />
Proc. of the International Workshop on Logic Synthesis, MCNC North Carolina,<br />
USA, mai 1991.<br />
[87] R.Lipsett, C.Schaefer, C.Ussery, VHDL: Hardware Description and Design, Kluwer<br />
Aca<strong>de</strong>mic Publishers, 1989.<br />
[88] K. L. McMil<strong>la</strong>n, J. Schwalbe, “Formal Verification of the Encore Gigamax Cache<br />
Consistency Protocol”, in International Symposium on Shared Memory Multiprocessors,<br />
1991.<br />
[89] J. C. Madre, J. P. Billon, “Proving Circuit Correctness using Formal Comparison<br />
Between Expected and Extracted Behaviour”, in Proc. of the 25th DAC, Anaheim<br />
CA, USA, juillet 1988.<br />
[90] J.C.Madre, J.P.Billon, O.Cou<strong>de</strong>rt, M.Currat, “ApplyinganAutomatedTheorem<br />
ProvingTechniquetoHardwareVerification”,inProgress in Computer Ai<strong>de</strong>d Design,<br />
Volume 5, Ablex Publishing, USA, 1990.<br />
[91] J. C. Madre, O. Cou<strong>de</strong>rt, M. Currat, A. Debreil, C. Berthet, “The Formal Verification<br />
Chain at BULL”, in Proc. of the EUROASIC Conference, Paris, France, juin<br />
1990.<br />
[92] J. C. Madre, O. Cou<strong>de</strong>rt, “Automating the Diagnosis and the Rectification of Design<br />
Errors with PRIAM”, in Proc. of ICCAD’89, Santa C<strong>la</strong>ra, USA, novembre 1989.