Molecular beam epitaxial growth of III-V semiconductor ... - KOBRA

5.5 Self-Assembled InGaAs QDs Embedded in Si Matrix
is driven by the thermal mismatch in Si/InAs system. At the end of the growth
of QDs the system experience nearly local equilibrium state, with mist strain
relieved totally by MD array. However, during cooling down the substrate temperature
to the room temperature and due to the thermal mismatch, InAs will
shrink faster than Si by keeping constant structure volume. Therefore, introduction
of thermal stress during cooling down to room temperature resulted in extra
mist dislocations generation. Similar strain analysis done for samples with 1
and 2 MLs InAs QDs coverage and showed almost same observations as 4 MLs
InAs sample. As a conclusion from strain study, a fully relaxed InAs QDs formation
has been observed and mostly with semi-coherent dots formation. However,
the lattice strain relaxation is released by dislocation loops localized along the
InAs/Si interface consisting of perfect 60 ◦ -type dislocations. The thermal stress
is released by SFs and MTs generation during cool down process, which have been
observed in some cases.
5.5 Self-Assembled InGaAs QDs Embedded in Si
Matrix
In order to reduce the lattice mismatch between III-V quantum dots and silicon,
indium concentration in In x Ga 1−x As QDs was reduced to 50 %. The lattice mismatch
is measured by the mist parameter (f) dened by Eq. 5.13. However, the
mist parameter (f ) is a function of the alloy composition (x) in ternary semiconductor
compounds like In x Ga 1−x As [90]. The lattice constant of In x Ga 1−x As can
be obtained by Eq. 5.14. Therefore, for 50 % indium composition the lattice constant
was calculated in Eq. 5.15, by direct substitution of the lattice constant in
Eq. 5.15 into Eq. 5.13. The lattice mismatch between In 0.5 Ga 0.5 As and Si matrix
is around 7.5 %, which is almost 40 % less than the lattice mismatch in InAs QDs
embedded into a Si matrix. After our standard ex-situ and in-situ surface preparation
used in Sec. 5.4, a silicon buer layer with 50 nm thickness was grown on
exactly oriented n-type Si (100) substrate at 700 ◦ C followed by 10 minutes PGA
at 800 ◦ C. These steps were applied for all samples investigated in this section.
The optimization of dierent growth parameters, such as In 0.5 Ga 0.5 As coverage,
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