Molecular beam epitaxial growth of III-V semiconductor ... - KOBRA

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Heteroepitaxial Growth of III-V Semiconductor on Silicon Substrates Where T and T 0 are the nal and initial temperatures of the growth system respectively, α S and α S are the temperature dependent coecients of thermal expansion of substrate and layer [14, 50]. The actual dependence of the thermal expansion coecients on temperature of GaAs are small enough that can be ignored to rst order, leading to simplied expression for the thermal mismatch strain as a function of the total change in reactor temperature ∆T [14]. ɛ t = (α S − α L ) ∆T (3.17) For GaAs lms on Si substrates at typical reactor growth temperature of 600 ◦ C, the total tensile strain developed during the cool-down process to room temperature will be 0.26 %. This strain is signicantly less than the total material mismatch strain for this material system, but still signicant enough to cause some important eects in the heteroepitaxial layers. Because this strain develops as the epitaxial layers are cooled from the growth temperature , dislocation relaxation mechanisms are much less ecient at relieving the resulting strain [14]. In addition, the dierence in thermal expansion coecients also aects the rate in which the two crystals contract during post growth or cool-down. Because the silicon substrate contracts less than the GaP epilayer, tensile strain may accumulate. Dislocation glide velocity decreases exponentially with decreasing temperature, and thus the residual thermal expansion strain that remains in a heteroepitaxial layer at room temperature can be as high as 90 % of the total thermal mismatch [51]. However, this trapped tensile strain can lead to the formation of micro-cracks in the epitaxial layer, with micro-crack nucleation behavior governed by an eective critical cracking thickness, thermal mismatch strain can also act to reduce the critical thickness of the grown layer [52]. Some practical ways to account for thermal mismatch strain in the III-V/Si material system have been proposed. For example, slower cooling rates after growth can encourage additional tensile strain reduction by pre-existing mist dislocations, although practical considerations limit how slowly temperature can be reduced [50]. Growth or device fabrication on reduced areas can increase the total thickness of the epitaxial layers that can be grown without crack formation [53, 54]. 40
3.4 Challenges of Heteroepitaxial Growth of III-V on Silicon Experimentally, if the epilayer is thick, the additional tensile strain can result in micro-cracking. In GaAs/Si, such cracks do not typically appear until the GaAs layer is in the range of 3 − 5 µm [55]. It is unknown at what thickness micro-cracking will occur in the GaP/Si system for example, but it is not expected to be an issue when GaP thickness do not exceed 1 µm, such as is the case in the work reported here. 3.4.4 Planar Defects Associated to Polar on Non-Polar Epitaxy An unavoidable issue of III-V/Si heteroepitaxy is the integration of polar and non-polar heterointerface. However, a complete understanding of polar on nonpolar epitaxy is a critical challenge for successful III-V semiconductor compound integration. Silicon, being made up of a single atomic species, forming purely covalent chemical bonds with zero net dipole moments, is a non-polar crystalline material. On the other hand, III-V like InAs, made up of both In and As atoms whose ionic bonds possess a signicant net dipole moment, is a so-called polar crystalline material; the interface between two such materials presents a number of challenges that must be taken into account. It was proposed that if the rst III-V atomic plane adjacent to the silicon bulk substrate were a perfect atomic plane, a large electrical charge would be induced [56]. To neutralize the interface charge, rearrangement of atoms may result, creating an environment of III-V island formations. Growing at low temperature with a layer by-layer growth mode, referred to as migration enhanced epitaxy (MEE), was used to address this issue. This growth technique proved indispensable for previous successful GaAs/Ge work [57]. The polar/non-polar charge neutrality dilemma is nearly impossible to monitor except by observation of possible post-epitaxy eects, such as the formation of interfacial planar defects such as: antiphase domain boundaries (APBs), stacking faults (SFs) and microtwin (MT) defects. The goal of this work, therefore, is the suppression of these heterointerface-driven defects through the proper surface preparation of the Si substrates and optimization of the growth and nucleation conditions of the III- 41
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Molecular Beam Epitaxial Growth of
Page 4 and 5: Gutachter (Supervisors): 1. Prof. D
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Page 12 and 13: CONTENTS 3.4.4 Planar Defects Assoc
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Page 16 and 17: Introduction thesis a detailed stud
Page 18 and 19: Introduction 1.1.2 Thesis Approach
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MBE Growth of Self-Assembled InAs a
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MBE Growth of InAs and InGaAs Quant
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Optimization of MEE and MBE growth
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Conclusions substrates, respectivel
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REFERENCES [8] J. M. Gerard, O. Cab
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REFERENCES [29] http://www.wmi.badw
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REFERENCES [49] M. R. Brenner: GaP/
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REFERENCES [66] Y. Ishida, T. Takah
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REFERENCES [84] A. Garcia, C. M. Ma
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REFERENCES [100] M. Felici, P. Gall
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REFERENCES [116] H. Usui, H. Yasuda
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REFERENCES [133] Grassman, T. J. Br
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Conferences Contributions: Tariq Al
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Nomenclature
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REFERENCES symbol Descriptions γ f
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like to thank all member of the Ins
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REFERENCES Erklärung Hiermit versi
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Molecular beam epitaxial growth of III-V semiconductor ... - KOBRA

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