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Reliability Characteristics of Rare Earth Oxides and their Gate Stacks on Germanium
Substrate.
M.S. Rahman 1 , E.K.Evangelou 1,* , I.I.Androulidakis 1 , S.Galata 2 G.Mavrou 2 , A.Dimoulas 2 and D.F Anagnostopoulos 3
1 Lab. of Electronics-Telecommunications & Applications, Dept of Physics, University of Ioannina, 45110-Greece.
2 MBE Laboratory, Institute of Materials Science, NCSR “Demokritos”, 153 10 Athens
3 Dept. of Materials Science & Engineering, University of Ioannina, 45110-Greece
*eevagel@uoi.gr
Abstract:
The critical dimensions of MOS devices are now reaching even the atomic scale, e.g., while the physical gate length is
measured in nanometers, the thinnest layers (e.g. gate dielectrics) are of the order of a few Å, i.e. few nano layers. Mobility
enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. Thus, Ge is a
promising material for nanoscale MOSFETs due to its high mobility, hence high source of injection velocity which translates
into higher drive current and smaller gate delay. High mobility MOSFETs have been recently demonstrated on bulk Ge with
high-κ gate dielectric and metal gates. However, one of the biggest challenges for the development of a Ge MOSFET is to
find appropriate passivating materials and methodologies for the Ge/high-k interfaces. Germanium oxynitride is frequently
used as a passivating interlayer in combination with HfO 2 . Unfortunately, it is considered to be insufficient since the
electrical characteristics of the capacitors are non ideal and the corresponding field effect transistors underperform, probably
due to a high density of interface defects.
Rear earth oxides (RE) are currently widely investigated for the replacement of SiO 2 as a gate insulator in advanced
MOSFETs. One would expect to reduce charge trapping and the stress induced leakage current (SILC) thus improving the
reliability of corresponding device. They are also potential candidates as dielectrics because of the relatively high-κ(~ 20).
However, it remains a challenge to avoid formation of a low-k interfacial layer between a RE oxide and the Ge substrate.
In the present work we studied reliability issues in various RE oxide gate stacks such as: a) HfO2/Dy 2 O 3 /Ge and b)
CeO 2 /Ge. In all cases both n- and p-type Ge(100) substrates were used while, the top metal for the definition of MOS devices
was Pt. Typical thickness of the oxide layer(s) is around 10nm. The density of the interface states (D it ) was ranging from the
low 10 12 eV -1 cm -2 up to the mid 10 13 eV -1 cm -2 . The evolution of D it with field in the oxide (E ox ) at room temperature is
presented and discussed. The dynamics of the interfacial defects were also studied and are illustrated together with the results
about the (de)trapping dynamics of bulk oxide defects. Finally the stress induced leakage current (SILC) measurements are
presented. It is shown that SILC is negligible at low E ox values, while at higher fields it follows a power law.
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