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Stress and Performance Characteristics of Novel Polysilicon TFTs
D. C. Moschou 1 , M. A. Exarchos 2 , D. N. Kouvatsos 1 , G. J. Papaioannou 2 and A. T. Voutsas 3
1 Institute of Microelectronics, NCSR Demokritos, Agia Paraskevi 15310, Greece
2 Physics Department, National and Kapodistrian University of Athens, Athens 15784, Greece
3 LCD Process Technology Laboratory, Sharp Labs of America, 5700 NM Pacific Rim Blvd, Camas, WA 98607, USA
*dmoschou@imel.demokritos.gr
Abstract SLS ELA polysilicon TFTs fabricated in novel films of different microstructure and texture, were investigated. The
parameter statistics indicate that the TFT performance depends on film quality and asperities, in conjunction with the grain
boundary trap density. The drain current transients, upon TFT switch from OFF to ON state, showed oxide polarization,
related to film asperities. DC hot carrier stress was applied, indicating a reliability dependence on polysilicon structure and
differences in degradation mechanisms for various TFT technologies.
1. Introduction
Low temperature polycrystalline silicon thin film transistors (LTPS TFTs) are essential for large area electronic circuits
and VLSI technology, as well as for high performance flat panel display applications [1]. Along with the increased
performance characteristics of future LTPS TFTs, high reliability should also be achieved for the fabrication of commercial
products to be possible. With the recent polysilicon crystallization process breakthroughs, using various excimer laser anneal
(ELA) methods such as sequential lateral solidification (SLS), the TFT performance has substantially increased [2-4].
Variations of the SLS technique allow the manufacturing of films with excellent intragrain quality and grains of different
shapes and sizes. The performance and reliability of TFTs are known to depend on the polysilicon film microstructure [5].
In this work we investigate the characteristics of top gate TFTs in polysilicon films, fabricated with various SLS
crystallization methods, yielding different film textures and structures of grain boundaries. The device parameter statistics,
the transient current behaviour and the TFT degradation under hot carrier stress are studied.
2. Experimental
The TFTs studied were fabricated in 50 nm thick polysilicon films, formed by ELA crystallization of a:Si, using
variations of the SLS technique, with the laser beam being shaped by an appropriate mask. For our 2-shot samples the mask
consists of two columns, slightly offset from each other, each with a set of parallel slits. This kind of polysilicon films has
rectangular shaped crystal domains. A variation of this procedure is the 2 N -shot, where the laser beam is divided in a number
of regions, with sets of slits, orthogonal to each other. This technique results in grains with excellent internal crystalline
quality, as each spot is irradiated many times, and again rectangular grains. In this work, TFTs in 2 6 -shot films have been
studied. In the procedure termed MN the mask consists again of sets of slits orthogonal to each other. The difference of this
procedure with the 2 N -shot one is that in the latter technique one set of the slits irradiates the same region, and so does not
contribute to lateral growth, but increases the intragrain quality. On the contrary, in the MN procedure all of the sets
advance the lateral growth front, resulting in larger domain sizes of lower intragrain quality. There are also procedures where
the beam shaping masks consist of arrays of dots, and so the lateral growth of the film begins from the dots and progresses
radially, resulting in square or hexagonal shaped crystal domains separated by grain boundaries.
The TFTs had a non-self-aligned top-metal-gate structure and a PECVD SiO2 gate dielectric. The TFTs and SIMOX
MOSFETs, used as reference, were characterized and stressed using a HP4140B semiconductor analyzer. The I ds -V gs transfer
characteristics were taken with V ds of 0.1 V, and the device parameters were extracted; furthermore, we applied Levinson
analysis to calculate the grain-boundary trap densities of the TFTs. The drain current transients upon application of gate bias
pulses, when unstressed TFTs are switched from OFF- to ON- state, were also investigated. A DC hot carrier stress (V gs , V ds )
of (5 V, 10 V) was applied for a maximum of 16 hours, for TFTs fabricated in all of the above described samples.
3. Results and Discussion
A. Device characteristics
V th
(V)
(cm 2 /Vsec)
S
(mV/decade)
N t
(cm -3 )
SIMOX -0,57 322,15 0,11
2-shot -1,87 282,31 0,39 6,57×10 11
2 6 -shot 0,21 187,33 0,16 3,81×10 11
Dot 30HEX -1,31 163,01 0,23 5,01×10 11
50SQ 0,62 198,14 0,21 9,04×10 11
MN #1 -1,03 235,40 0,17 3,4×10 11
#7 -0,95 321,96 0,19 3,77×10 11
#8 -0,20 289,08 0,15 3,03×10 11
Table I: Device parameter average values
From AFM images of the films, we observe
an increased number of high protrusions for the 2 6 -
shot film. The height of the protrusions becomes
significantly smaller for the 2-shot film. In the
MN film we again observe high protrusions, but
much more sparsely distributed within the film
surface. In Table I we can see the average values of
the threshold voltage V th , the field-effect mobility
, the subthreshold slope S and the grain-boundary
trap density N t as obtained by Levinson analysis of
the measured devices. We examined two different
variations of the Dot technology and four of the
MN technology, the differences, for the Dot
technologies, being the hexagonal crystal domains
for the 30Hex samples and the square ones for the 50Sq samples, while for the MN technologies being the crystal domain
size. We can see that the largest mobility values, approaching the ones of SIMOX devices, are obtained for MN TFTs,
followed closely by 2-shot and then by 2 6 -shot and Dot ones. This order of the different technologies with decreasing
mobility can be attributed to the combination of two factors: the grain-boundary trap density N t and the surface asperities.
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