xxiii πανελληνιο ÏƒÏ Î½ÎµÎ´ÏÎ¹Î¿ Ï†Ï ÏƒÎ¹ÎºÎ·Ï‚ στερεας καταστασης & επιστημης ...

The Effect of Sub-boundaries on the Performance and Reliability of ovel SLS ELA
Polysilicon TFTs
M. A. Exarchos 1* , D. C. Moschou 2 , D. N. Kouvatsos 2 , G. J. Papaioannou 1 and A. T. Voutsas 3
1 Physics Department, National and Kapodistrian University of Athens, Athens 15784, Greece
2 Institute of Microelectronics, NCSR Demokritos, Agia Paraskevi 15310, Greece
3 LCD Process Technology Laboratory, Sharp Labs of America, 5700 NM Pacific Rim Blvd, Camas, WA 98607, USA
*mexarcho@phys.uoa.gr
Abstract Polysilicon TFTs fabricated in a film crystallized with a novel SLS ELA technique, yielding rectangular crystal
domains much larger than the TFT channel dimensions, were investigated. The TFT channels were oriented both along the
preferential direction and vertical to it, thus probing the sub-boundary effects of both directions. DLTS assessment was
conducted on unstressed TFTs in order to probe the film’s defect nature. DC hot carrier stress was applied for both channel
orientations, in order to elucidate the effect of the crystallization procedure and its resulting microstructure on the reliability
of the devices. A dimensional optimization of the TFTs was found.
1. Introduction
In this work we investigate the application of a novel SLS ELA polysilicon crystallization method [1-3], termed MN,
for top gate TFTs oriented along both preferential and non-preferential directions. Through DLTS analysis the defect nature
of the polysilicon film is probed. The relation between process characteristics and device reliability is elucidated through hotcarrier
stress. An optimization of the TFT performance through variation of the channel length was attempted.
2. Experimental
The TFTs studied were fabricated in polysilicon film formed by ELA crystallization of a:Si, using an SLS technique
termed MN. In this procedure the mask (Fig. 1) consists of sets of slits orthogonal to each other. The grains grow first in the
Y direction (via the "M" patterns) and, then, sub-boundaries within these grains are swept in the X direction (via the "N"
patterns), which is therefore the preferential direction. This results in large domain sizes but of lower intragrain quality than
other, multi-shot techniques. A SEM image of the polysilicon film can be seen in Fig. 2. Since the crystal domain is much
larger than the TFT channel, no hard grain boundaries should be included in either direction. However, nanoscale subboundaries
(evidenced by features like protrusions and hillocks) are present in both directions, known to affect the TFT
performance [3]. DLTS assessment was conducted on unstressed TFTs, immediately after the device transition from OFF- to
ON-state. Drain current spectra I d (T) were monitored and measured. Devices were stressed and characterized in both
directions. The hot-carrier stress was applied for a maximum duration of 16 hours.
3. Results and Discussion
DLTS measurements were conducted under the same bias conditions for unstressed TFTs. DLTS spectra magnitudes
I d (T) are considerably higher for the devices having the channel aligned to X direction, than in Y direction. This is so
because the respective energy barrier height E B of the grain boundaries is lower (Fig. 3) [4]. For X-oriented TFTs,
E B (X)=0.026eV and for Y-oriented ones, E B (Y)=0.043eV. Further decomposed, the DLTS spectra for each oriented TFT
disclosed three thermally activated contributions corresponding to three discrete traps (Fig. 4). Their activation energies were
calculated in the range 0.39eV-0.53eV. The Arrhenius signatures closest to the detected defects are associated with hole traps
originating from dislocations and rapid thermal annealing (RTA) defects.
To probe the effect of the sub-boundaries on the reliability of our TFTs we applied hot-carrier stress, with
V gstress =V dstress /2, on both channel orientations. A more severe degradation in the X orientation is revealed even for milder
stress conditions (Fig. 5), due to the softer grain boundaries. Also, the parallel shift of the I DS -V GS characteristics in the Y
direction is attributed to charges injected in the gate oxide, while in the X direction the curve distortion implies severe
interface degradation.
In Figs. 6, 7 we see that for channel lengths larger or smaller than 1.2m the performance seems to deteriorate. The
increasing S with increasing L is attributed to more sub-boundaries included within the channel, while its increase with
decreasing L is an electrical effect, ascribed to the increased channel charge in the subthreshold regime [5] due to the
additional drain bias control of the channel region. These two mechanisms define the optimum TFT channel length for our
crystallization process.
4. Conclusions
SLS ELA polysilicon TFTs fabricated in films crystallized with a novel SLS ELA technique termed MN yielding
large rectangular crystal domains were studied, with the TFT channels oriented along the preferential and the non-preferential
direction. The DLTS analysis of the devices showed larger energy barrier height in the Y direction. Discrete traps deep in
polysilicon energy gap were detected, originating from dislocations and rapid thermal annealing defects. TFT degradation
seemed to be less pronounced in the Y direction, due to the harder sub-boundaries obstructing the stress current. The main
degradation mechanism for the X direction was interface state generation, while for the Y direction the gate oxide charge
injection. An optimum channel length was found, defined both by the sub-boundary characteristics and by electrical effects.
References
[1] A.T. Voutsas, IEEE Trans. Electron Dev. ED-50 (2003) 1494.
[2] M.A. Crowder, M. Moriguchi, Y. Mitani and A.T. Voutsas, Thin Solid Films 427 (2003) 101.
[3] A.T. Voutsas, A. Limanov and J.S. Im, J. Appl. Phys. 94 (2003) 7445.
[4] Y.Morimoto et al, Journal of Electrochemical Society, 144, 7, pp 2495-2501, (1997)
[5] A. G. Lewis et al, IEDM '89 Proc., pp. 349-352 (1999).
68