xxiii Ïανελληνιο ÏÏ Î½ÎµÎ´Ïιο ÏÏ ÏÎ¹ÎºÎ·Ï ÏÏεÏÎµÎ±Ï ÎºÎ±ÏαÏÏαÏÎ·Ï & εÏιÏÏÎ·Î¼Î·Ï ...
xxiii Ïανελληνιο ÏÏ Î½ÎµÎ´Ïιο ÏÏ ÏÎ¹ÎºÎ·Ï ÏÏεÏÎµÎ±Ï ÎºÎ±ÏαÏÏαÏÎ·Ï & εÏιÏÏÎ·Î¼Î·Ï ...
xxiii Ïανελληνιο ÏÏ Î½ÎµÎ´Ïιο ÏÏ ÏÎ¹ÎºÎ·Ï ÏÏεÏÎµÎ±Ï ÎºÎ±ÏαÏÏαÏÎ·Ï & εÏιÏÏÎ·Î¼Î·Ï ...
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C/ C ox<br />
1,0<br />
0,8<br />
0,6<br />
0,4<br />
0,2<br />
0,0<br />
-4 -2 0 2 4<br />
V gate<br />
[V]<br />
Figure 2: High frequency C-V curves of a MOS device containing Pt nanoparticles embedded in the HfO 2 /SiO 2 interface for<br />
V gate =(-1.5)-(+1.5) V (●), (-2)-(+2) V (▲), (-2.5)-(+2.5) V (▼), (-3)-(+3) V (►), (-3.5)-(+3.5) (*) and sample without dots<br />
for V gate =(-4)-(+4) V (■).<br />
V<br />
FB<br />
(V)<br />
3.0<br />
square pulse<br />
2.5<br />
2.0<br />
1.5<br />
1.0<br />
0.5<br />
DV max<br />
=4.43 V<br />
0.0<br />
-0.5<br />
-1.0<br />
-1.5<br />
-2.0<br />
-2.5<br />
2 4 6 8 10<br />
(V)<br />
V gate-pulse<br />
Figure 3: Flat-band voltage shift versus gate voltage pulse (Vgate-pulse). Pulse duration was 100ms.<br />
It is assumed that the extracted ΔV FB is only due to the application of the square pulse. Electron (hole) charging initiates at<br />
voltage pulses of about +5 V (–5 V) and further increases until +9 V (–9 V). The maximum memory window obtained is<br />
ΔV FB =4.43V.<br />
We have fabricated MOS device stacks that are composed of: a thin injection SiO 2 layer, high-density of Pt nanoparticles<br />
deposited thereon and a 37nm-thick HfO 2 control oxide. Structural and electrical studies reveal that these structures are<br />
suitable for non-volatile memory devices with low-voltage injection.<br />
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