xxiii πανελληνιο ÏƒÏ Î½ÎµÎ´ÏÎ¹Î¿ Ï†Ï ÏƒÎ¹ÎºÎ·Ï‚ στερεας καταστασης & επιστημης ...

Degradation at the Back Polysilicon Interface During Hot Carrier Stress in Double Gate
Polysilicon TFTs
Giannis P. Kontogiannopoulos 1 , Filippos V. Farmakis 1 , Dimitrios N. Kouvatsos 1 and Apostolos T. Voutsas 2
1 Institute of Microelectronics, NCSR Demokritos, Agia Paraskevi 15310, Greece
2 LCD Process Technology Laboratory, Sharp Labs of America, 5700 NM Pacific Rim Blvd, Camas, WA 98607, USA
*gkonto@imel.demokritos.gr
Abstract
Degradation phenomena due to hot carrier stress conditions were investigated in double gate polysilicon thin film transistors
fabricated by sequential lateral solidification (SLS). We varied the hot carrier stress conditions at the front-gate channel by
applying various voltages at the back-gate. Thus, we investigated the device electrical performance under such stress
regimes.
1. Introduction
Low temperature polysilicon TFTs have attracted much interest, as they have many advantages, such as high field-effect
mobility. However, due to low-temperature processes that have been developed, numerous defects exist in grains and grain
boundaries of the poly-Si channel. This disadvantage has been mainly overcome by using a variety of recently developed
crystallization processes such as sequential lateral solidification excimer laser annealing (SLS ELA) [1]. However, one of the
major issues associated with polysilicon TFTs is their reliability [1,2]. The scope of this work is to provide evidences for
degradation mechanisms at the back interface of the device, via the aid of fully depleted double-gate (DG) polysilicon TFTs.
2. Experimental
The investigated TFTs were n-channel DG devices fabricated in 50 nm thick polysilicon films on top of a 50 nm thick
PECVD SiO 2 insulator. A front gate 30 nm thick PECVD SiO 2 insulator was also deposited. The polysilicon films were
formed by the SLS ELA technique [3]. TFTs in such films can be oriented in a preferential direction, with the channel
parallel to the grain boundaries. Active regions were then patterned and defined, resulting in a structure composed from very
long crystal grains separated by grain boundaries.
The TFTs were characterized and stressed using a HP4140B semiconductor analyzer. The drain current (I DS ) vs front gate
voltage (V GF ) characteristics at a given back-gate voltage (V GB ) were taken, at 300 K, in the linear region, with V DS = 0.1 V.
The maximum transconductance G m,max was extracted by the slope of a line fitted to the I DS -V GF characteristics at a given
V GB , drawn in linear scale, while the intercept with the horizontal axis yielded the extrapolated threshold voltage V th . DC hot
carrier stress conditions (V GF,stress , V DS,stress , V GB,stress ) were applied for durations up to 27000 s, the I DS -V GF curves were
recorded at the end of each stress cycle with various values of V GB and the device parameters were extracted each time.
3. Results and discussion
DG devices provide the advantage to examine electrical performance as a function of the opposite gate biasing and thus to
explore the possibility of investigating TFT properties at both the back and the front polysilicon/SiO 2 interfaces. Figure 1
shows the quantities G m,max and V th of front interface as a function of the back-gate (BG) voltage. We observe that V th
continuously decreases as the BG voltage increases [4,5], suggesting that the polysilicon film appears fully depleted in this
range of measurements. G m,max exhibits its highest value when V GB is around 0 V, indicating that the back interface is
depleted. When V GB becomes positive, G m,max decreases due to the increase of the inversion layer thickness and consequently
the increase of the trap density “seen” by electrons in the bulk polysilicon film. In contrast, when V GB becomes negative, the
vertical electric field at the front interface is intensified, leading to an enhancement of the scattering mechanisms of carriers
at the front poly/SiO 2 interface, which is reflected in the G m,max decrease [4,5].
In order to study the induced hot-carrier phenomena in DG transistors and, more specifically, to investigate the possible
back-interface degradation during aging, stress regimes with accumulated, inverted and depleted back interface were utilized.
The front-gate bias during stress was chosen so as to ensure the same lateral electric field.
The G m,max degradation is shown in Figure 2. Regarding the V GB,stress = - 3 V and V GB,stress = 0 V cases, we observe that the
same G m,max degradation occurs, when the measurements are performed at accumulated back interface condition. It can be
assumed that interface state generation at the front interface is identical for both stress regimes. Moreover, for V GB,stress = 0 V,
the G m,max degradation, as measured with inverted back interface, is identical to the degradation measured with the back
interface accumulated, whereas for V GB,stress = - 3 V, ∆G m,max is dependent on the back-gate voltage used in the measurements.
Thus, it seems that, for the V GB,stress = 0 V case, the back interface does not add any electrical contribution to the front channel
conduction, suggesting minor damage at the back interface, while for V GB,stress = - 3 V the back interface seems to deteriorate
during stressing. Another interesting observation is that for V GB,stress = 3 V a different G m,max degradation mechanism is
observed, which is dependent on the back-gate voltage used in the measurements.
Figures 3 and 4 demonstrate the V th shift during stress measured with the BG voltage at accumulation and inversion for the
three aging regimes. From figure 3 it can be seen that, in all cases, V th drifts towards negative values. Moreover, in the case of
V GB,stress = 3 V, the ∆V th negative shift appears enhanced. In contrast to that case, in the case of V GB,stress = - 3 V, the threshold
voltage V th exhibits a negative shift followed by a positive one. From figure 4, in the case of V GB,stress = 3 V, we observe that
V th drifts monotonically towards positive values. When V GB,stress =-3 V is applied, V th shifts negatively and, after a certain
stress duration, it takes high positive values. For V GB,stress = 0 V, the threshold voltage continuously decreases.
In the case of V GB,stress = - 3 V, we mention an elevated dispersion of V th at higher BG voltages (i.e. V GB = 3 V). This implies
that the degradation takes place mainly at the back interface of the device. Considering that the back-gate is negatively
charged, it is reasonable to believe that hot-holes created by impact ionization at the drain edge region can be easily
70