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V th
(V)
G m,max
/G m,max0
(%)
I d
(mA)
Figure 2: a) Switch-ON drain current transient amplitude, under strong
inversion conditions. b) Drain current transients of MxN TFTs with W / L = 8
m / 2 m. The -state bias was 2.9V and the OFF-state bias was -1.1V with its
The small N t value is essential to
obtain large field-effect mobility,
but the effect of surface roughness
should not be neglected, since it
can degrade the performance of a
TFT, as in 2 6 -shot TFTs.
Furthermore, lower S and N t
values indicate higher grain
quality for 2 6 -shot and MN
TFTs.
As far as the drain current
transient analysis is concerned,
we made the following
observations. The switch-ON
transients exhibit a complex
duration 100msec.
behavior where overshoot and undershoot effect coexist (Fig.2a). Although overshoot transients relax through stretched
exponential law [6], given by I d (t) = D d (0)exp[-(t/) ] (where I d is the drain current transient, is the characteristic time
and is a stretch factor), undershoot transients, for temperature values higher than 300K, obey a double stretched exponential
law indicating that the relaxation process is governed by a complex mechanism (Fig.2b). The observed undershoot effect
could be ascribed to a gate oxide polarization phenomenon rather than to a carrier trapping / detrapping process. Among these
crystallization technologies the gate oxide polarization effect is expected to be more pronounced for the 2 6 -shot samples,
since the effect of protrusions is the largest. It is worth noticing that the mobility values for these samples are rather low
considering their crystalline quality, indicating that the role of polarization is detrimental.
B. Stress behavior
0,9
0,8
0,7
0,6
0,5
0,4
0,3
0,2
0,1
0,0
-0,1
-0,2
20
10
0
-10
-20
0,0
-2,0x10 -4
-4,0x10 -4
-6,0x10 -4
-8,0x10 -4
100 150 200 250 300 350 400
T (K)
MxN#1 W=8m L=2m
2-shot W=8m L=2m
2 6 -shot W=8m L=2m
Dot 30hex W=6m L=2m
SIMOX W=8m L=2m
1 10 100 1000 10000 100000
stress time (sec)
MxN#1 W=8m L=2m
2-shot W=8m L=2m
2 6 -shot W=8m L=2m
Dot 30hex W=6m L=2m
SIMOX W=8m L=2m
2 6 -shot W/L=8/5
MxN#8 W/L=4/0.8
MxN#8 W/L=16/8
Figure 4: Evolution of V th with stress
time.
1 10 100 1000 10000 100000
stress time (sec)
Figure 5: Evolution of G m,max /G m,max (0) with
stress time.
I d (mA)
0,0
-5,0x10 -5
-1,0x10 -4
-1,5x10 -4
-2,0x10 -4
200K
300K
400K
Stretched exp. fit
Double stretched exp. fit
10 -3 10 -2 10 -1
In Fig. 4 we can see the evolution of the threshold voltage with the
stress time for devices from all of our technologies. The smallest
threshold voltage variation can be observed for MN and Dot samples,
probably because of the minimal presence of surface asperities within the
channel region, minimizing the local field enhancement caused by the
protrusions. On the other hand, the 2 6 -shot and SIMOX samples show a
logarithmic increase of the threshold voltage with stressing time,
indicating a mechanism of injection of hot electrons into the gate oxide.
As far as the 2-shot sample is concerned, we see an initial rapid increase
of the threshold voltage, indicating a swift injection of hot electrons in
the oxide, followed by a decrease, possibly due to added effects of
interface degradation entailing positive charges.
In Fig. 5 we see the evolution of the transconductance with the
stress time. TFTs in MN, 2-shot and Dot samples show an initial
increase of the value of G m,max followed by a degradation. This behavior
could be attributed to “channel shortening” of the devices [7], with initial
overshoot caused by increased stress-induced damage located near the
drain region. In SIMOX devices we observe a delayed increase of
G m,max , indicating slower near-drain damage. A continuous G m,max
degradation is only observed for 2 6 -shot devices, where the injection
could be more uniform along the channel.
4. Conclusions
Polysilicon TFTs fabricated in novel SLS ELA films of different
intragrain quality, surface roughness and grain boundary trap density
were characterized. Apart from the grain quality, film asperities seem to
have a significantly negative effect on the device performance. A gate
oxide polarization effect was observed and related to the polysilicon
protrusions. The DC hot carrier stress indicated a dependence of the
device reliability on the microstructure of the polysilicon and a possible
channel shortening effect present for some of the TFT technologies.
Acknowledgment
The authors acknowledge financial support through the research project PENED 3ED550, administered by the Greek
General Secretariat for Research and Technology.
References
[1] T. Matsuo and T. Muramatsu, Proc. SID Intern. Symposium, p. 856, 2004.
[2] S. D. Brotherton, D. J. McCulloch, J. B. Clegg, and J. P. Gowers, IEEE Trans. Electron Dev. ED-40 (1993) 407.
[3] M.A. Crowder, M. Moriguchi, Y. Mitani and A.T. Voutsas, Thin Solid Films 427 (2003) 101.
[4] A.T. Voutsas, A. Limanov and J.S. Im, J. Appl. Phys. 94 (2003) 7445.
[5] H. Toutah et al., Microelectr. Reliab. 43 (2003) 1531.
[6] G.J. Papaioannou, M.A. Exarchos, D.N. Kouvatsos and A.T. Voutsas, Appl. Phys. Lett. 87 (2005) 252112.
[7] A.T. Hatzopoulos et al., IEEE Trans. Electron Dev. ED-52 (2005) 2182.
t (sec)
75