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Successive Layer Charging of Si Nanocrystals in a Double-Layer Nanocrystal
Structure within SiO 2
M. Theodoropoulou, A. Salonidou and A. G. Nassiopoulou*
IMEL/NCSR Demokritos, Terma Patriarchou Grigoriou, Aghia Paraskevi, 153 10 Athens, Greece
*A.Nassiopoulou@imel.demokritos.gr
Two-dimensional arrays of Si nanocrystals within SiO 2 constitute a distributed charge storage medium
with better immunity to tunnel oxide defects compared with the polycrystalline silicon continuous
charging medium used in conventional non-volatile memory devices [1]. However, when tunnel oxide
thickness goes below ~5 nm, data retention fails to fulfill the 10-years criterion set for non-volatility. In
order to overcome this problem, a two-layer structure, with one layer composed of very small
nanocrystals (diameter below ~3 nm) and a second one on top with larger nanocrystals (diameter above
~5 nm) was proposed [2]. In this case, due to quantum confinement, the small dots show a band offset
compared with the larger dots, which acts as a barrier for carrier leakage to the substrate.
In this work we fabricated such a structure using low pressure chemical vapor deposition of
amorphous silicon (α-Si) on a thin tunnel oxide on Si, followed by high temperature-thermal
oxidation/annealing and we investigated its charging properties. The fabrication conditions were
presented in detail elsewhere [3].
The following processing steps were used. First, p-type silicon wafers with a resistivity of 1-2 Ω.cm
were oxidized at 850 o C for 8 min producing an approximately 3.5 nm thick thermal oxide. An
approximately 9.5 nm thick silicon film was deposited on top of the thermal oxide, by LPCVD at
580 o C, 300 mTorr, for 3 min. The samples were oxidized at 900 o C for 25 min producing an
approximately 13 nm thick thermal oxide, on top of a 2.5 nm thick silicon nanocrystal layer. In order to
reduce the thickness of the top oxide layer, the samples were chemically etched in a 2% HF solution,
resulting in a 1.5 nm thick top oxide layer. High temperature annealing was performed in N 2 at 900 o C
for 30 min. The resulting structure contains one layer of silicon nanocrystal within two SiO 2 layers. By
repeating the same procedure, a second silicon nanocrystal layer is grown, with a size of 3.5 nm and a
control oxide of 10 nm. Finally the samples were annealed in N 2 at 900 o C for 30 min. For electrical
characterization an aluminum gate metal was deposited and patterned and an ohmic contact was
formed on the back side of the wafer. The two-layered silicon nanocrystal MOS structure is shown
schematically in Fig.1.
To investigate the charging properties of the silicon nanocrystal layers, capacitance-voltage
(C-V) measurements were performed at 1MHz, at room temperature, by applying positive and negative
gate pulses of different height and width on the gate without discharging the structure between applied
pulses. Fig. 2 shows C-V curves of a fresh capacitor compared to those obtained after application of
positive and negative gate pulses. The pulse width was 15 s and the pulse height step 0.5 V. When a
positive or a negative gate pulse is applied, a positive or negative shift in the flatband voltage is
obtained, indicative of charging the silicon nanocrystal layers with electrons (holes) respectively. This
charging is due to injection of electrons (holes) from the silicon substrate to the nanocrystal layers
through the tunnel oxide. In the presence of the two layers, charging of the first layer is first completed,
resulting in a first saturation step in the flat band voltage shift ΔV FB , and charging of the second layer
(second saturation step) occurs at a higher voltage. The same occurs at negative applied pulses,
corresponding to hole charging. A maximum positive shift of 2.1 V and negative shift of -2.8 V were
obtained for maximum end voltages of ±8 V.
Fig. 3 shows the flatband voltage shift ΔV FB as a function of the applied positive or negative
gate pulse height. The pulse width was 15 s and the gate pulse step was 0.5 V. Two very distinct steps
separated by about 1.5 V and 2.5 V are observed. These steps correspond to the successive charging of
the first and second nanocrystal layer [4]. We see that full charging of the first nanocrystal layer is
completed at approximately +4 V/-4 V, while the second nanocrystal layer is fully charged at
approximately +8V/-8V.
In conclusion, we demonstrated multilevel charge storage (+4V/-4V, +8V/-8V) in a doublelayer
Si nanocrystal MOS structure, fabricated by LPCVD deposition of α-Si and subsequent thermal
oxidation. The flatband voltage shift of the structure as a function of the applied positive/negative gate
pulse height indicated the successive charging of the two silicon nanocrystal layers by electron(hole)
injection respectively. These results are very promising for application in multi-bit memory devices.
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