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forwarded to the back interface during stress. Thus, the damaged region is located at the back drain-polysilicon interface. As
hot-hole induced damage becomes severe, V th increases due to the induced interface state density. At the front interface
possibly hot-electrons damage the polysilicon/SiO 2 interface and/or the grain boundaries, thus degrading G m,max . When the
device was subjected to a stress condition with V GB,stress = 3 V, V th decreased for V GB = - 3 V and increased for V GB = 3 V.
Moreover, G m,max degradation is larger than for previous stress conditions. Since, for V GB,stress >0, the vertical electric field is
enhanced, it promotes hot-hole injection at the front interface, while hot electrons are accelerated towards the back interface.
Indeed, under this condition hot-holes and hot-electrons acquire more energy to be directly injected in the front- and in the
BG oxide respectively. As a result, hot-hole induced interface state generation is enhanced at the front interface and electron
injection at the BG oxide provokes an additional negative V th shift, when measured at V GB = - 3 V. In the case of V GB,stress = 0
V, V th is decreased by the same amount for all BG voltages. In this case, the V th decrease appears in the subthreshold region.
This is possible if we consider that the positive charge in the back oxide increases during aging. Therefore, it is suggested that
moderate hot-hole injection occurs in the BG oxide with no observable interface state generation phenomena. Regarding the
front interface degradation, since the G m,max variation is identical to that for the stress condition V GB,stress = - 3 V, we propose
that the observed degradation arises from hot-electron damage at the poly/SiO 2 interface and/or grain boundaries.
Maximum transconductance, G m,max
[A/V]
1.3x10 -5
1.2x10 -5
2
1.1x10 -5
1.0x10 -5
0
9.0x10 -6
8.0x10 -6
-2
7.0x10 -6
-3 -2 -1 0 1 2 3
Back gate voltage, V GB
[V]
Figure 1: Maximum transconductance and threshold
voltage variation for front gate operation as a function
back-gate biasing. All measurements are performed
in the linear regime (V DS =0.1 V).
Threshold voltage, V th
[V]
-(G m,max
/G m,0
)/G m,0
(%)
50 V GB,stress
= -3 V
40
V GB,stress
= 0 V
V GB,stress
= 3 V
30
20
10
0
10 0 10 1 10 2 10 3 10 4
Stress time [s]
Figure 2: Maximum transconductance variation (%) for
the three stress conditions (differing back-gate stress bias) of
measured at V GB = - 3 V (filled marks) and V GB = 3 V
(open marks).
∆V th
[V]
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
V GB,stress
= -3 V
V GB,stress
= 0 V
V GB,stress
= 3 V
measured at
V GB
= -3 V
10 0 10 1 10 2 10 3 10 4
Stress time [s]
∆V th
[V]
1.5
1.2
0.9
0.6
0.3
0.0
-0.3
-0.6
-0.9
V GB,stress
= -3 V
V GB,stress
= 0 V
V GB,stress
= 3 V
measured at
V GB
= +3 V
10 0 10 1 10 2 10 3 10 4
Stress time [s]
Figure 3: Threshold voltage shift for the three stress
Figure 4: Threshold voltage shift for the three stress
conditions (differing back-gate stress bias) measured at
conditions (differing back-gate stress bias) measured at
V GB =- 3 V. V GB = 3 V.
Conclusions
It was suggested that stress conditions with negative back-gate voltage enhance hot-hole injection in the BG oxide and
hot-electron induced phenomena at the front polysilicon/SiO 2 interface. In contrast, for positive BG during aging, hot-hole
injection at the front interface revealed serious degradation with combined hot-electron induced effects at the back interface.
References
[1] Farmakis FV, Brini J, Kamarinos G and Dimitriadis CA. IEEE Electron Dev. Lett. 22 (2001) 74.
[2] Cristoloveanu S. Microelectronics Reliability, 37, (1997), 1003.
[3] Voutsas AT. IEEE Trans. Electron Devices 50 (2003) 1494.
[4] Farmakis FV, Kouvatsos DN, Voutsas AT, Moschou DC, Kontogiannopoulos GP, and Papaioannou GJ. J. Electrochem.
Soc. to be published.
[5] Banna SR, Chan PCH, Chan M, Fung SKH and Ko PK. IEEE Trans. Electr. Dev., vol. 45, (1998), 206-212.
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