27.03.2013 Views

Cisco Broadband Cable Command Reference Guide

Cisco Broadband Cable Command Reference Guide

Cisco Broadband Cable Command Reference Guide

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

Chapter 5 <strong>Cable</strong> CPE <strong>Command</strong>s<br />

OL-1581-05<br />

Table 5-4 show controllers cable-modem Field Descriptions<br />

show controllers cable-modem<br />

Field Description<br />

TX BD ring: Indicates the memory location of the beginning of buffer information for the<br />

transmit buffer descriptor ring.<br />

tx_count If tx_count is 0, or if tx_head and tx_tail are equal and there is no change for<br />

a period of time, it means there are packets stuck on the ring. This condition<br />

may be caused by the CMTS not giving grants.<br />

tx_head Indicates current head transmit packet descriptor.<br />

head_txp The next packet descriptor to get used, along with its index.When head_txp<br />

and tail_txp are the same, the transmit queue is empty.<br />

tx_tail Indicates current tail transmit packet descriptor.<br />

tail_txp The next packet descriptor to get sent, along with its index. When head_txp<br />

and tail_txp are the same, the transmit queue is empty.<br />

TX PD ring: Indicates the memory location of the beginning of buffer information for the<br />

transmit packet descriptor ring.<br />

tx_head_pd Indicates current head packet descriptor.<br />

tx_tail_pd Indicates current tail packet descriptor.<br />

ehdr Extended MCNS header.<br />

MIB Statistics<br />

DS fifo full Number of times the downstream input first-in first-out (FIFO) buffer<br />

became full on the router.<br />

rerequests Number of times a bandwidth request generated by the router was not<br />

responded to by the CMTS.<br />

DS mac msg overruns Number of times the router’s DMA controller had a downstream MAC<br />

message and there were no free MAC message buffer descriptors to accept<br />

the message.<br />

DS data overruns Number of times the router’s DMA controller had downstream data and there<br />

were no free data PDU buffer descriptors to accept the data.<br />

Qualified maps Number of times a MAP message passed all filtering requirements and was<br />

received by the router.<br />

Qualified syncs Number of times a timestamp message was received by the router.<br />

CRC fails Number of times a MAC message failed a cyclic redundancy check (CRC).<br />

HDR chk fails Number of times a MAC header failed its 16-bit CRC check. The MAC<br />

header CRC is a 16-bit Header Check Sequence (HCS) field that ensures the<br />

integrity of the MAC header even in a collision environment.<br />

Data pdus Total number of data protocol data units (PDUs) of all types received by the<br />

router.<br />

Mac msgs Number of MAC messages received by the router.<br />

Valid hdrs Number of valid headers received by the router, including PDU headers,<br />

MAC headers, and headers only.<br />

Global control and Used to reset the BCM3300 chip.<br />

status:<br />

interrupts: Hexadecimal values of the pending IRQ interrupt and IRQ mask.<br />

<strong>Cisco</strong> <strong>Broadband</strong> <strong>Cable</strong> <strong>Command</strong> <strong>Reference</strong> <strong>Guide</strong><br />

5-73

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!