cifX Communication Interfaces Real-Time Ethernet - Hilscher
cifX Communication Interfaces Real-Time Ethernet - Hilscher
cifX Communication Interfaces Real-Time Ethernet - Hilscher
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Device Connections and Switches 235/274<br />
9.10.4 Pin Assignment for PCI Express Bus CIFX 100EH-RE\CUBE<br />
Only for: CIFX 100EH-RE\CUBE (x1 = One Lane) 6<br />
PCI Express Bus X2 (Side B) PCI Express Bus X1 (Side A)<br />
Pin Name Description Pin Name Description<br />
B1 n. u. (not used) A1 PRSNT1# Hot-Plug presence detect<br />
B2 n. u. (not used) A2 n. u. (not used)<br />
B3 n. u. (not used) A3 n. u. (not used)<br />
B4 GND Ground A4 GND Ground<br />
B5 n. u. (not used) A5 JTAG-TCK JTAG Test Clock<br />
B6 n. u. (not used) A6 JTAG-TDI JTAG Test Data Input<br />
B7 GND Ground A7 JTAG-TDO JTAG Test Data Output<br />
B8 3V3 3,3V Power A8 JTAG-TMS JTAG Test Mode Select Input<br />
B9 JTAG-TRST# JTAG Test Reset A9 3V3 3,3V Power<br />
B10 3V3AUX 3,3V Power A10 3V3 3,3V Power<br />
B11 n. u. (not used) A11 PERST# PCIe Reset<br />
B12 n. u. (not used) A12 GND Ground<br />
B13 GND Ground A13 PCIe_CLK+ PCIe Clock<br />
B14 PCIe_TP Transmitter Lane,<br />
A14 PCIe_CLK- differential pair<br />
B15 PCIe_TN differential pair A15 GND Ground<br />
B16 GND Ground A16 PCIe_RP Receiver Lane,<br />
B17 PRSNT2# Hot-Plug presence detect A17 PCIe_RN differential pair<br />
B18 GND Ground A18 GND Ground<br />
B19 n. u. (not used) A19 n. u. (not used)<br />
B20 n. u. (not used) A20 n. u. (not used)<br />
B21 n. u. (not used) A21 n. u. (not used)<br />
B22 n. u. (not used) A22 n. u. (not used)<br />
B23 GND Ground A23 n. u. (not used)<br />
B24 IO_SYNC0 / <strong>Real</strong>-<strong>Time</strong> <strong>Ethernet</strong> SYNC 8 A24 n. u. (not used)<br />
IO_SYNC1 / 3,3V 7<br />
B25 GND Ground A25 n. u. (not used)<br />
B26 SPI_CS# ID Chip Select A26 n. u. (not used)<br />
B27 SPI_MOSI ID Slave In A27 n. u. (not used)<br />
B28 SPI_MISO ID Slave Out A28 n. u. (not used)<br />
B29 SPI_CLK ID Clock A29 n. u. (not used)<br />
B30 GND Ground A30 n. u. (not used)<br />
B31 n. u. (not used) A31 n. u. (not used)<br />
B32 n. u. (not used) A32 n. u. (not used)<br />
Key<br />
Table 83: Pin Assignment for PCI-Express-Bus CIFX 100EH-RE\CUBE<br />
6 Pinning A19 to A32 / B19 to B32 not standard conform [bus spec 3, page 73-74].<br />
7 If at the SYNC connector J3 the jumper is set, the IO_SYNC signal is transferred<br />
to the PCI Express Bus X2 pin B24 (jumper on pin1-pin2(J3): IO_SYNC0, pin2-<br />
pin3(J3): IO_SYNC1). If no jumper is set, the signal is 3,3V static High (with Pull-up).<br />
Refer to section Pin Assignment SYNC Connector, J3, on page 228.<br />
8 in 3V3 logic.<br />
<strong>cifX</strong> <strong>Communication</strong> <strong>Interfaces</strong> <strong>Ethernet</strong> | Installation, Operation and Hardware Description<br />
DOC060501UM30EN | Revision 30 | English | 2011-06 | Released | Public © <strong>Hilscher</strong>, 2006-2011
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