cifX Communication Interfaces Real-Time Ethernet - Hilscher

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Table 47: Slot Number (Card ID) in the Device Assignment 197
Table 48: Overview LEDs Real-Time Ethernet Systems 200
Table 49: System LED 201
Table 50: LEDs EtherCAT Master 202
Table 51: LED State Definition for EtherCAT Master for the RUN and ERR LEDs 202
Table 52: LEDs EtherCAT Slave 203
Table 53: LED State Definition for EtherCAT Slave for the RUN and ERR LEDs 204
Table 54: LEDs EtherNet/IP Scanner (Master) 205
Table 55: LEDs EtherNet/IP Adapter (Slave) 206
Table 56: LEDs Open Modbus/TCP 207
Table 57: LEDs Powerlink Controlled Node/Slave 208
Table 58: LED State Definition for Powerlink Controlled Node/Slave for the BS/BE LEDs 209
Table 59: LEDs PROFINET IO-RT Controller 210
Table 60: LEDs PROFINET IO-RT-Device 211
Table 61: LEDs SERCOS III Master 212
Table 62: LED State Definition for SERCOS III Master for the STA and ERR LEDs 213
Table 63: LEDs SERCOS III Slave 214
Table 64: LED State Definition for SERCOS III Slave for the S3 LED 214
Table 65: Ethernet Pin Assignment at the RJ45 Socket for cifX or AIFX 219
Table 66: Ethernet Connection Data 219
Table 67: Use of Hubs and Switches 220
Table 68: Pin Assignment Mini-B USB Connector 221
Table 69: Rotary Switch for PCI 104 Slot Number, S1 222
Table 70: Rotary Switch for Slot Number (Card ID), S1 223
Table 71: Switch Position Rotary Switch Slot Number (Card ID) 223
Table 72: Pin Assignment for Cable Connector Ethernet X4 or X304 226
Table 73: Pin Assignment for Cable connector DIAG X3 or X303 227
Table 74: Pin Assignment for SYNC Connector, X51 228
Table 75: Pin Assignment for SYNC Connector, J3 228
Table 76: SYNC Connector: SYNC Signal, Connector, Max. Cable Length 229
Table 77: Meaning of the SYNC Signals for each Protocol 229
Table 78: Pin Assignment at the Bus 230
Table 79: References to the Standard Bus Specifications 230
Table 80: Pin Assignment for Mini PCI Bus, X1 232
Table 81: Pin Assignment Mini PCI Express Bus / SYNCr, X1/X2 (from HW-Rev. 6 on) 233
Table 82: Assignment of the Pins 6, 28, 48 (+1V5) (HW-Rev. 1 to 5) 234
Table 83: Pin Assignment for PCI-Express-Bus CIFX 100EH-RE\CUBE 235
Table 84: Pin Assignment for PC/104-Bus, X1 (Control Signals used on the 8 Bit Connector) 236
Table 85: Pin Assignment for PC/104-Bus, X2 (Used Control Signals on the Expansion Connector) 237
Table 86: Technical Data CIFX 50-RE 238
Table 87: Technical Data CIFX 50E-RE 239
Table 88: Technical Data CIFX 80-RE 240
Table 89: Technical Data CIFX 90-RE\F 241
Table 90: Technical Data CIFX 90E-RE\F 242
Table 91: Technical Data CIFX 100EH-RE\CUBE 243
Table 92: Technical Data CIFX 104C-RE, CIFX 104C-RE-R, CIFX 104C-RE\F, CIFX 104C-RE-R\F 244
Table 93: Technical Data CIFX 104-RE, CIFX 104-RE-R, CIFX 104-RE\F, CIFX 104-RE-R\F 245
Table 94: Technical Data AIFX-RE 246
Table 95: Technical Data AIFX-DIAG 246
Table 96: PCI IDs cifX Communication Interfaces on the PCI Bus 247
Table 97: Technical Data EtherCAT Master Protocol 248
Table 98: Technical Data EtherCAT Slave Protocol 249
Table 99: Technical Data EtherNet/IP Scanner (Master) Protocol 250
cifX Communication Interfaces Ethernet | Installation, Operation and Hardware Description
DOC060501UM30EN | Revision 30 | English | 2011-06 | Released | Public © Hilscher, 2006-2011