cifX Communication Interfaces Real-Time Ethernet - Hilscher

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Device Connections and Switches 236/274 9.10.5 Pin Assignment for PC/104 Bus Only for: CIFX 104-RE, CIFX 104-RE-R , CIFX 104-RE\F, CIFX 104-RE-R\F The used control signals of the PC/104 bus are given in the tables below. Pin Assignment for PC/104-Bus, X1 Pin (X1) A B 1 GND 2 SD7 RESET 3 SD6 +5V 4 SD5 IRQ9 5 SD4 6 SD3 7 SD2 8 SD1 9 SD0 10 IOCHRDY GND 9 11 AEN SMEMW 12 SA19 SMEMR 13 SA18 14 SA17 15 SA16 16 SA15 17 SA14 18 SA13 19 SA12 20 SA11 21 SA10 IRQ7 22 SA9 IRQ6 23 SA8 IRQ5 24 SA7 IRQ4 25 SA6 IRQ3 26 SA5 27 SA4 28 SA3 29 SA2 +5V 30 SA1 31 SA0 GND 32 GND GND Table 84: Pin Assignment for PC/104-Bus, X1 (Control Signals used on the 8 Bit Connector) 9 Differs from the standard [bus spec 9, page B-2]. cifX Communication Interfaces Ethernet | Installation, Operation and Hardware Description DOC060501UM30EN | Revision 30 | English | 2011-06 | Released | Public © Hilscher, 2006-2011
Device Connections and Switches 237/274 Important: Avoid dual-port memory access errors It is mandatory that the host CPU always uses the IOCHNRDY (pin A10) signal, otherwise these results in wrong data read from the dual-port memory or dual-port memory write accesses are being ignored. - The maximum value for accesses can not be specified. - For maximum performance, the IOCHNRDY signal must always be evaluated by the host CPU. - If you use a host CPU that can not use the IOCHNRDY (A10) signal, then contact our technical support. Pin Assignment for PC/104-Bus, X2 Pin (X2) C D 0 GND GND 1 SBHE MEMCS16 2 3 IRQ10 4 IRQ11 5 IRQ12 6 IRQ15 7 IRQ14 8 9 10 11 SD8 12 SD9 13 SD10 14 SD11 15 SD12 16 SD13 +5V 17 SD14 18 SD15 GND 19 GND Table 85: Pin Assignment for PC/104-Bus, X2 (Used Control Signals on the Expansion Connector) The pin assignment described in Table 84 and Table 85 originates from the standard [bus spec 9, page B-2] (refer to section References to the Bus Specifications on page 230). cifX Communication Interfaces Ethernet | Installation, Operation and Hardware Description DOC060501UM30EN | Revision 30 | English | 2011-06 | Released | Public © Hilscher, 2006-2011
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Introduction 15/274 1.2.7 EtherCAT
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Page 211 and 212: LED Descriptions 211/274 8.10 PROFI
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Page 235: Device Connections and Switches 235
Page 239 and 240: Technical Data 239/274 10.1.2 CIFX
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Page 257 and 258: Technical Data 257/274 10.3.10 SERC
Page 259 and 260: Annex 259/274 11.2 EtherCAT Summary
Page 261 and 262: Annex 261/274 11.3 Disposal of Wast
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Page 267 and 268: Lists 267/274 Table 100: Technical
Page 269 and 270: Glossary 269/274 Coil Device Descri
Page 271 and 272: Glossary 271/274 netX Configuration
Page 273 and 274: Glossary 273/274 XML XML means Exte
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cifX Communication Interfaces Real-Time Ethernet - Hilscher

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