cifX Communication Interfaces Real-Time Ethernet - Hilscher

Device Connections and Switches 237/274
Important: Avoid dual-port memory access errors
It is mandatory that the host CPU always uses the IOCHNRDY (pin A10)
signal, otherwise these results in wrong data read from the dual-port memory
or dual-port memory write accesses are being ignored.
- The maximum value for accesses can not be specified.
- For maximum performance, the IOCHNRDY signal must always be
evaluated by the host CPU.
- If you use a host CPU that can not use the IOCHNRDY (A10) signal, then
contact our technical support.
Pin Assignment for PC/104-Bus, X2
Pin (X2) C D
0 GND GND
1 SBHE MEMCS16
2
3 IRQ10
4 IRQ11
5 IRQ12
6 IRQ15
7 IRQ14
8
9
10
11 SD8
12 SD9
13 SD10
14 SD11
15 SD12
16 SD13 +5V
17 SD14
18 SD15 GND
19 GND
Table 85: Pin Assignment for PC/104-Bus, X2 (Used Control Signals on the Expansion
Connector)
The pin assignment described in Table 84 and Table 85 originates from the
standard [bus spec 9, page B-2] (refer to section References to the Bus
Specifications on page 230).
cifX Communication Interfaces Ethernet | Installation, Operation and Hardware Description
DOC060501UM30EN | Revision 30 | English | 2011-06 | Released | Public © Hilscher, 2006-2011