Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.7.4 PCISTS2—PCI Status Register (Device 2)Address Offset:Default Value:Access:Size:06h−07h0090hRO, R/WC16 bitsPCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort andPCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by theIGD.BitDescription15 Detected Parity Error (DPE)⎯RO. Hardwired to 0. The IGD does not detect parity.14 Signaled System Error (SSE)⎯RO. Hardwired to 0. The IGD never asserts SERR#.13 Received Master Abort Status (RMAS)⎯RO. Hardwired to 0. The IGD never gets a Master Abort.12 Received Target Abort Status (RTAS)⎯RO. Hardwired to 0. The IGD never gets a Target Abort.11Signaled Target Abort Status (STAS)—RO. Hardwired to 0. The IGD does not use target abortsemantics.10:9 DEVSEL# Timing (DEVT) —RO. Hardwired to 00; Not applicable.8Data Parity Detected (DPD) ⎯RO. Hardwired to 0. Parity Error Response is hardwired to disabled(and the IGD does not do any parity detection).Fast Back-to-Back (FB2B)—RO. Hardwired to 1. The IGD accepts fast back-to-back when the7transactions are not to the same agent.6 User Defined Format (UDF)—RO. Hardwired to 0.5 66 MHz PCI Capable (66C).—RO. Hardwired to 0; Not applicable.CAP LIST—RO. Hardwired to 1 to indicate that the register at 34h provides an offset into the4function’s PCI Configuration space containing a pointer to the location of the first item in the list.3:0 Reserved.3.7.5 RID2—Revision Identification Register (Device 2)Address Offset:Default Value:Access:Size:08hSee table belowRO8 bitsThis register contains the revision number of the IGD.Bit7:0DescriptionRevision Identification Number—RO. This is an 8-bit value that indicates the revisionidentification number for the IGD.02h = A-2 Stepping104 Intel ® 82865G/82865GV GMCH Datasheet