IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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Register Description3.5.5 RID—Revision Identification Register (Device 0)Address Offset:Default Value:Access:Size:08hSee table belowRO8 bitsThis register contains the revision number of the GMCH Device 0.Bit7:0DescriptionsRevision Identification Number (RID)—RO. This is an 8-bit value that indicates the revisionidentification number for the GMCH Device 0.02h = A-2 stepping3.5.6 SUBC—Sub-Class Code Register (Device 0)Address Offset:Default Value:Access:Size:0Ah00hRO8 bitsThis register contains the Sub-Class Code for the GMCH Device 0.Bit7:0DescriptionsSub-Class Code (SUBC)—RO. This is an 8-bit value that indicates the category of bridge for theGMCH.00h = Host bridge.3.5.7 BCC—Base Class Code Register (Device 0)Address Offset:Default Value:Access:Size:0Bh06hRO8 bitsThis register contains the Base Class Code of the GMCH Device 0.Bit7:0DescriptionsBase Class Code (BASEC)—RO. This is an 8-bit value that indicates the Base Class Code forthe GMCH.06h = Bridge device.60 Intel ® 82865G/82865GV GMCH Datasheet
Register Description3.5.8 MLT—Master Latency Timer Register (Device 0)Address Offset:Default Value:Access:Size:0Dh00hRO8 bitsDevice 0 in the GMCH is not a PCI master. Therefore, this register is not implemented.BitDescriptions7:0 Reserved.3.5.9 HDR—Header Type Register (Device 0)Address Offset:Default Value:Access:Size:0Eh00hRO8 bitsThis register identifies the header layout of the configuration space. No physical register exists atthis location.Bit7:0DescriptionsPCI Header (HDR)—RO. This field always returns 0 to indicate that the GMCH is a single functiondevice with standard header layout.Intel ® 82865G/82865GV GMCH Datasheet 61
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Intel ® 865G/865GV ChipsetDatashee
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Contents1 Introduction.............
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3.8 PCI-to-CSA Bridge Registers (De
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5.5.3 Synchronous Display .........
Page 10 and 11: Tables1 General Terminology .......
Page 14: This page is intentionally left bla
Page 20 and 21: Introduction1.4 Intel ® 82865G GMC
Page 24: Introduction1.4.7 Display Interface
Page 27 and 28: Signal Description2.1 Host Interfac
Page 29 and 30: Signal DescriptionSignal Name Type
Page 31 and 32: Signal Description2.2.2 DDR SDRAM C
Page 33 and 34: Signal Description2.5 AGP Interface
Page 35 and 36: Signal Description2.5.4 AGP Strobes
Page 37 and 38: Signal DescriptionSignal Name Type
Page 39 and 40: Signal Description2.5.7 Intel ® DV
Page 41 and 42: Signal Description2.7 Clocks, Reset
Page 44 and 45: Signal Description2.10 GMCH Sequenc
Page 46 and 47: Signal Description2.12 Full and War
Page 48 and 49: Register DescriptionTermReservedReg
Page 50 and 51: Register Description3.3 Routing Con
Page 52 and 53: Register DescriptionIf the Bus Numb
Page 54 and 55: Register Description3.4.2 CONFIG_DA
Page 56 and 57: Register DescriptionTable 6.DRAM Co
Page 58 and 59: Register Description3.5.3 PCICMD—
Page 62 and 63: Register Description3.5.10 APBASE
Page 64 and 65: Register Description3.5.14 AGPM—A
Page 66 and 67: Register DescriptionNotes on Pre-Al
Page 68 and 69: Register Description3.5.17 FPLLCONT
Page 70 and 71: Register DescriptionAs an example,
Page 72 and 73: Register Description3.5.20 SMRAM—
Page 74 and 75: Register Description3.5.22 ACAPID
Page 76 and 77: Register Description3.5.24 AGPCMD
Page 78 and 79: Register Description3.5.26 APSIZE
Page 80 and 81: Register Description3.5.29 LPTT—A
Page 82 and 83: Register Description3.5.31 GMCHCFG
Page 84 and 85: Register Description3.5.32 ERRSTS
Page 86 and 87: Register Description3.5.34 SKPD—S
Page 88 and 89: Register Description3.6.1 VID1—Ve
Page 90 and 91: Register Description3.6.4 PCISTS1
Page 92 and 93: Register Description3.6.8 MLT1—Ma
Page 94 and 95: Register Description3.6.14 IOBASE1
Page 96 and 97: Register Description3.6.17 MBASE1
Page 100: Register Description3.6.22 ERRCMD1
Page 105 and 106: Register Description3.7.6 CC—Clas
Page 107 and 108: Register Description3.7.11 MMADR—
Page 109 and 110: Register Description3.7.16 CAPPOINT
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Register Description3.7.22 PMCAP—
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Register Description3.8 PCI-to-CSA
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Register Description3.8.3 PCICMD3
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Register Description3.8.5 RID3—Re
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Register Description3.8.11 SBUSN3
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Register Description3.8.15 SSTS3—
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Register Description3.8.17 MLIMIT3
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Register Description3.8.20 BCTRL3
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Register Description3.9 Overflow Co
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Register Description3.9.4 PCISTS6
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Register Description3.9.9 BAR6—Me
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Register DescriptionThe remaining 7
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Register Description3.10.3 DRT—DR
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Register DescriptionBit6:4Descripti
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System Address MapSystem Address Ma
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System Address Map4.2 Compatibility
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System Address Map4.3 Extended Memo
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System Address MapPCI Memory Addres
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Functional DescriptionFunctional De
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Functional Description5.2 System Me
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Functional Description5.2.2.1 Dynam
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Functional DescriptionTable 21. DRA
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Functional DescriptionTable 23. DRA
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Functional Description5.2.6 Configu
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Functional Description5.3.1 GMCH AG
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Functional Descriptiondown controll
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Functional Description5.3.6 Support
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Functional Description5.4.1 3D Engi
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Functional DescriptionTexture Forma
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Functional DescriptionTexture Map B
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Functional DescriptionDepth BufferT
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Functional Description5.4.3 Video E
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Functional Description5.4.5 PipesSc
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Functional DescriptionIntegrated RA
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Functional DescriptionDirect YUV fr
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Functional Description• System—
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Functional Description5.8 ClockingT
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Electrical CharacteristicsElectrica
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Electrical CharacteristicsTable 36.
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Electrical Characteristics6.5 DC Pa
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Page 193 and 194:
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Electrical Characteristics6.6.3 DAC
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Ballout and Package InformationBall
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Ballout and Package InformationFigu
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Ballout and Package InformationTabl
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Page 209 and 210:
Ballout and Package Information7.2
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TestabilityTestability 8In the GMCH
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Testability8.2 XOR Chain Definition
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TestabilityTable 45. XOR Chain 1 (3
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Intel ® 82865GV GMCHIntel ® 82865
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Intel ® 82865GV GMCH9.3 Intel ® 8
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Intel ® 82865GV GMCHGMCHCFG—GMCH
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Intel ® 82865GV GMCH BalloutIntel
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Intel ® 82865GV GMCH BalloutFigure
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Intel ® 82865GV GMCH BalloutTable
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Intel ® 82865GV GMCH TestabilityIn
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Intel ® 82865GV GMCH Testability11
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Intel ® 82865GV GMCH TestabilityTa
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IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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