Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Signal Description2.2.2 DDR SDRAM Channel BThe following DDR signals are for DDR channel B.Signal Name Type DescriptionSCMDCLK_B[5:0]SCMDCLK_B[5:0]#SCS_B[3:0]#SMAA_B[12:0]SMAB_B[5:1]SBA_B[1:0]SRAS_B#SCAS_B#SWE_B#SDQ_B[63:0]SDM_B[7:0]SDQS_B[7:0]SCKE_B[3:0]OSSTL_2OSSTL_2OSSTL_2OSSTL_2OSSTL_2OSSTL_2OSSTL_2OSSTL_2OSSTL_2I/OSSTL_2OSSTL_2I/OSSTL_2OSSTL_2Differential DDR Clock: SCMDCLK_Bx and SCMDCLK_Bx# aredifferential clock output pairs. The crossing of the positive edge ofSCMDCLK_Bx and the negative edge of SCMDCLK_Bx# is used tosample the address and control signals on the SDRAM. There are threepairs to each DIMM.Complementary Differential DDR Clock: These are thecomplementary Differential DDR Clock signals.Chip Select: These signals select particular SDRAM components duringthe active state. There is one SCS_Bx# for each SDRAM row, toggled onthe positive edge of SCMDCLK_Bx.Memory Address: These signals are used to provide the multiplexedrow and column address to the SDRAM.Memory Address Copies: These signals are identical to SMAA_B[5:1]and are used to reduce loading for Selective CPC (clock-per-command).Bank Select (Bank Address): These signals define which banks areselected within each SDRAM row. Bank select and memory addresssignals combine to address every possible location within an SDRAMdevice.Row Address Strobe: SRAS_B# is used with SCAS_B# and SWE_B#(along with SCS_B#) to define the SDRAM commands.Column Address Strobe: SCAS_B# is used with SRAS_B# andSWE_B# (along with SCS_B#) to define the SDRAM commands.Write Enable: SWE_B# is used with SCAS_B# and SRAS_B# (alongwith SCS_B#) to define the SDRAM commands.Data Lines: SDQ_B signals interface to the SDRAM data bus.Data Mask: When activated during writes, the corresponding datagroups in the SDRAM are masked. There is one SDM_Bx for every eightdata lines. SDM_Bx can be sampled on both edges of the data strobes.Data Strobes: Data strobes are used for capturing data. During writes,SDQS_Bx is centered in data. During reads, SDQS_Bx is edge alignedwith data. The following list matches the data strobe with the data bytes.Data Strobe Data ByteSDQS_B7 SDQ_B[63:56]SDQS_B6 SDQ_B[55:48]SDQS_B5 SDQ_B[47:40]SDQS_B4 SDQ_B[39:32]SDQS_B3 SDQ_B[31:24]SDQS_B2 SDQ_B[23:16]SDQS_B1 SDQ_B[15:8]SDQS_B0 SDQ_B[7:0]Clock Enable: SCKE_B[3:0] are used to initialize DDR SDRAM duringpower-up and to place all SDRAM rows into and out of self-refreshduring Suspend-to-RAM. SCKE_B[3:0] are also used to dynamicallypower down inactive SDRAM rows. There is one SCKE_Bx per SDRAMrow, toggled on the positive edge of SCMDCLK_Bx.Intel ® 82865G/82865GV GMCH Datasheet 31