Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.6.4 PCISTS1—PCI Status Register (Device 1)Address Offset: 06–07hDefault Value: 00A0hAccess:RO, R/WCSize:16 bitsPCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated withprimary side of the virtual PCI-to-PCI bridge in the GMCH.BitDescriptions151413121110:98Detected Parity Error (DPE)—RO. Hardwired to 0. Parity is not supported on the primary side ofthis device.Signaled System Error (SSE)—R/WC.0 =Software clears this bit by writing a 1 to it.1 =GMCH Device 1 generated a SERR message over HI for any enabled Device 1 error condition.Device 1 error conditions are enabled in the ERRCMD, PCICMD1 and BCTRL1 registers.Device 1 error flags are read/reset from the ERRSTS and SSTS1 register.Received Master Abort Status (RMAS)—RO. Hardwired to 0. The concept of a master abortdoes not exist on primary side of this device.Received Target Abort Status (RTAS)—RO. Hardwired to 0. The concept of a target abort doesnot exist on primary side of this device.Signaled Target Abort Status (STAS)—RO. Hardwired to 0. The concept of a target abort doesnot exist on primary side of this device.DEVSEL# Timing (DEVT)—RO. The GMCH does not support subtractive decoding devices onbus 0. Therefore, this field is hardwired to 00 indicating that Device 1 uses the fastest possibledecode.Data Parity Detected (DPD)—RO. Hardwired to 0. Parity is not supported on the primary side ofthis device.Fast Back-to-Back (FB2B)—RO. Hardwired to 1. The AGP/PCI_B interface always supports fast7back-to-back writes.6 Reserved.5 66/60 MHz capability (CAP66)—RO. Hardwired to 1. The AGP/PCI bus is 66 MHz capable.4:0 Reserved.90 Intel ® 82865G/82865GV GMCH Datasheet