Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Signal Description2.7 Clocks, Reset, and Miscellaneous SignalsSignal Name Type DescriptionHCLKPHCLKNGCLKINDREFCLKRSTIN#PWROKEXTTS#TESTIN#ICMOSILVTTLILVTTLILVTTLILVTTLILVTTLIDifferential Host Clock In: These pins receive a low voltage differential hostclock from the external clock synthesizer. This clock is used by all of the GMCHlogic that is in the Host clock domain 0.7 V.66 MHz Clock In:. This pin receives a 66 MHz clock from the clock synthesizer.This clock is used by AGP/PCI and HI clock domains.NOTE: This clock input is required to be 3.3 V tolerant.Display Clock Input: This pin provides a 48 MHz input clock to the Display PLLthat is used for 2D/Video/Flat Panel and DAC.NOTE: This clock input is required to be 3.3 V tolerant.Reset In: When asserted this signal will asynchronously reset the GMCH logic.This signal is connected to the PCIRST# output of the ICH5. All AGP/PCI outputand bi-directional signals will also tri-state compliant to PCI Rev 2.0 and 2.1specifications. This input should have a Schmitt trigger to avoid spurious resets.NOTE: This input needs to be 3.3 V tolerant.Power OK: When asserted, PWROK is an indication to the GMCH that the corepower and GCLKIN have been stable for at least 10 µs.External Thermal Sensor Input: Open-Drain signal indicating an Over-Tempcondition in the platform. This signal should remains asserted for as long as theOver-temp Condition exists. This input pin can be programmed to activatehardware management of memory reads and writes and/or trigger softwareinterrupts.Test Input. This signal is used in the GMCH XOR test mode. See Chapter 8 foruse.Intel ® 82865G/82865GV GMCH Datasheet 41