Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.10.2 DRA—DRAM Row Attribute Register (Device 6, MMR)Address Offset:Default Value:Access:Size:0010h–0013h00hRO, R/W8 bits each registerThe DRAM Row Attribute registers define the page sizes to be used when accessing different rowsor pairs of rows. The minimum page size of 4 KB occurs when in single-channel mode and either128-Mb, x16 devices are populated or 256-Mb, x16 devices are populated. The maximum pagesize of 32 KB occurs when in dual-channel mode and 512-MB, x8 devices are populated. Eachnibble of information in the DRA registers describes the page size of a row or pair of rows. Whenin either of the dual-channel modes, only registers 10h and 11h are used. The page sizeprogrammed reflects the page size for the pair of DIMMS installed. When in single-channel mode,registers 10h and 11h are used to specify page sizes for channel A and registers 12h and 13h areused to specify page sizes for channel B. If the associated row is not populated, the field mustbe left at the default value.Row0, 1:0010hRow2, 3:0011hRow4, 5:0012hRow6, 7:0013h7 6 4 3 2 0Rsvd Row Attribute for Row 1 Rsvd Row Attribute for Row 07 6 4 3 2 0Rsvd Row Attribute for Row 3 Rsvd Row Attribute for Row 27 6 4 3 2 0Rsvd Row Attribute for Row 5 Rsvd Row Attribute for Row 47 6 4 3 2 0Rsvd Row Attribute for Row 7 Rsvd Row Attribute for Row 6BitDescription7 Reserved.Row Attribute for Odd-Numbered Row—R/W. This field defines the page size of the correspondingrow. If the associated row is not populated, this field must be left at the default value.000 = 4 KB6:4 001 = 8 KB010 = 16 KB011 = 32 KBOthers = Reserved3 Reserved.2:0Row Attribute for Even-Numbered Row—R/W. This field defines the page size of the correspondingrow. If the associated row is not populated, this field must be left at the default value.000 = 4 KB001 = 8 KB010 = 16 KB011 = 32 KBOthers = Reserved134 Intel ® 82865G/82865GV GMCH Datasheet