Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register DescriptionTermReservedRegistersDefault Valueupon a ResetIn addition to reserved bits within a register, the GMCH contains address locations in theconfiguration space of the Host-HI Bridge entity that are marked either “Reserved” or“Intel Reserved”. The GMCH responds to accesses to reserved address locations bycompleting the host cycle. When a reserved register location is read, a zero value isreturned. (reserved registers can be 8, 16, or 32 bits in size). Writes to reserved registershave no effect on the GMCH.Caution:DescriptionRegister locations that are marked as “Intel Reserved” must not be modifiedby system software. Writes to “Intel Reserved” register locations may causesystem failure. Reads to “Intel Reserved” register locations may return a nonzerovalue.Upon a reset, the GMCH sets all of its internal configuration registers to predetermineddefault states. Some register values at reset are determined by external strappingoptions. The default state represents the minimum functionality feature set required tosuccessfully bring up the system. Hence, it does not represent the optimal systemconfiguration. It is the responsibility of the system initialization software (usually BIOS) toproperly determine the SDRAM configurations, operating parameters and optionalsystem features that are applicable, and to program the GMCH registers accordingly.3.2 Platform Configuration StructureIn some previous chipsets, the GMCH and the I/O Controller Hub (ICHx) were physicallyconnected by PCI bus 0. From a configuration standpoint, both components appeared to be on PCIbus 0, which was also the system’s primary PCI expansion bus. The GMCH contained two PCIdevices while the ICHx bridge was considered one PCI device with multiple functions.In the 865G chipset platform, the configuration structure is significantly different. The GMCH andthe ICH5 are physically connected by a hub interface (HI); thus, from a configuration standpoint,HI is logically PCI bus 0. As a result, all devices internal to the GMCH and ICH5 appear to be onPCI bus 0. The system’s primary PCI expansion bus is physically attached to ICH5 and, from aconfiguration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge;therefore, it has a programmable PCI Bus number. Note that the primary PCI bus is referred to asPCI_A in this document and is not PCI bus 0 from a configuration standpoint. The AGP appears tosystem software to be a real PCI bus behind PCI-to-PCI bridges resident as devices on PCI bus 0.The GMCH contains four PCI devices within a single physical component. The configurationregisters for the four devices are mapped as devices residing on PCI bus 0.• Device 0: Host-HI Bridge/DRAM Controller. Logically this appears as a PCI device residingon PCI bus 0. Physically, Device 0 contains the standard PCI registers, SDRAM registers, theGraphics Aperture controller, configuration for HI, and other GMCH specific registers.• Device 1: Host-AGP Bridge. Logically this appears as a “virtual” PCI-to-PCI bridge residingon PCI bus 0. Physically, Device 1 contains the standard PCI-to-PCI bridge registers and thestandard AGP/PCI configuration registers (including the AGP I/O and memory addressmapping).• Device 2: Integrated Graphics Controller. Logically this appears as a PCI device residing onPCI bus 0. Physically, Device 2 contains the configuration registers for 3D, 2D, and displayfunctions.• Device 3: Communications Streaming Architecture (CSA) Port. Appears as a virtual PCI-CSA(PCI-to-PCI) bridge device• Device 6: Function 0: Overflow Device. The sole purpose of this device is to provideadditional configuration register space for Device 0.48 Intel ® 82865G/82865GV GMCH Datasheet