Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register DescriptionBit6:4DescriptionMode Select (SMS)—R/W. These bits select the special operational mode of the DRAM interface.The special modes are intended for initialization at power up. Note that FCSEN (fast CS#) must beset to 0 while SMS cycles are performed. It is expected that BIOS may program FCSEN topossible 1 only after initialization.000 =Post Reset state – When the GMCH exits reset (power-up or otherwise), the mode selectfield is cleared to 000.During any reset sequence, while power is applied and reset is active, the GMCH de-asserts allCKE signals. After internal reset is de-asserted, CKE signals remain de-asserted until thisfield is written to a value different than 000. On this event, all CKE signals are asserted.During suspend (S3, S4), GMCH internal signal triggers SDRAM controller to flush pendingcommands and enter all rows into Self-Refresh mode. As part of resume sequence, theGMCH will be reset – which clears this bit field to 000 and maintains CKE signals deasserted.After internal reset is de-asserted, CKE signals remain de-asserted until this fieldis written to a value different than 000. On this event, all CKE signals are asserted.001 =NOP Command Enable – All processor cycles to DRAM result in a NOP command on theDRAM interface.010 =All Banks Pre-charge Enable – All processor cycles to DRAM result in an “all banksprecharge” command on the DRAM interface.011 =Mode Register Set Enable – All processor cycles to DRAM result in a “mode register” setcommand on the SDRAM interface. Host address lines are mapped to SDRAM addresslines in order to specify the command sent. Host address HA[13:3] are mapped to memoryaddress SMA[5:1].100 =Extended Mode Register Set Enable – All processor cycles to SDRAM result in an “extendedmode register set” command on the SDRAM interface. Host address lines are mapped toSDRAM address lines in order to specify the command sent. Host address lines aremapped to SDRAM address lines in order to specify the command sent. Host addressHA[13:3] are mapped to memory address SMA[5:1].101 =Reserved110 =CBR Refresh Enable – In this mode all processor cycles to SDRAM result in a CBR cycle onthe SDRAM interface111 =Normal operation3:2 Reserved1:0DRAM Type (DT)—RO. This field is used to select between supported SDRAM types.00 = Reserved01 = Dual Data Rate SDRAMOther = Reserved.Intel ® 82865G/82865GV GMCH Datasheet 137