Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.8 PCI-to-CSA Bridge Registers (Device 3)This device is the virtual PCI-to-CSA bridge. This section contains the PCI configuration registerslisted in order of ascending offset address. Table 11 provides the register address map for thisdevice.Table 11. PCI-to-CSA Bridge Configuration Register Address Map (Device 3)AddressOffsetRegisterSymbolRegister Name Default Value Access00–01h VID3 Vendor Identification 8086h RO02–03h DID3 Device Identification 2573h RO04–05h PCICMD3 PCI Command 0000h RO,R/W06–07h PCISTS3 PCI Status 00A0h RO,R/WC08h RID3 Revision IdentificationSee registerdescriptionRO09 — Reserved — —0Ah SUBC3 Sub-Class Code 04h RO0Bh BCC3 Base Class Code 06h RO0Ch — Reserved — —0Dh MLT3 Master Latency Timer 00h RO,R/W0Eh HDR3 Header Type 01h RO0F–17h — Reserved — —18h PBUSN3 Primary Bus Number 00h R/W19h SBUSN3 Secondary Bus Number 00h R/W1Ah SUBUSN3 Subordinate Bus Number 00h R/W1Bh SMLT3 Secondary Bus Master Latency Timer 00h RO,R/W1Ch IOBASE3 I/O Base Address F0h RO,R/W1Dh IOLIMIT3 I/O Limit Address 00h RO,R/W1E–1Fh SSTS3 Secondary Status 02A0h RO,R/WC20–21h MBASE3 Memory Base Address FFF0h RO,R/W22–23h MLIMIT3 Memory Limit Address 0000h RO,R/W24–25h PMBASE3 Prefetchable Memory Base Limit Address FFF0h RO,R/W26–27h PMLIMIT3 Prefetchable Memory Limit Address 0000h RO,R/W28–3Dh — Reserved — —3Eh BCTRL3 Bridge Control 00h RO,R/W3Fh — Reserved — —40h ERRCMD3 Error Command 00h RO,R/W41–4Fh — Reserved — —50–53h CSACNTRL CSA Control 0E04 2802h RO,R/W54–FFh — Intel Reserved — —Intel ® 82865G/82865GV GMCH Datasheet 113