IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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Intel ® 82865GV GMCHATTBASE — Aperture Translation Table Register (Device 0)Address OffsetSize:B8–BBh32 bitsAMTT — AGP MTT Control Register (Device 0)Address OffsetSize:BC–BFh8 bitsLPTT — AGP Low Priority Transaction Timer Register (Device 0)Address OffsetSize:BDh8 bits9.3.1.2 Device 0 Register Bit DifferencesThe registers described in this section are in both the 82865G and 82865GV. However, some of theregister bits have different functions/operations between the two components. Only the bits that aredifferent are shown in this section. The remaining register bits are the same for both the 82865Gand 82865GV and are described in Chapter 3.GC—Graphics Control Register (Device 0)Address OffsetDefault ValueAccessSize:52h0000_0000bRO, R/W. R/W/L8 bitsBitsDescription3Integrated Graphics Disable (IGDIS) — RO. The GMCH’s Device 1 is disabled such that allconfiguration cycles to Device 1 flow through to the hub interface. Also, the Next_Pointer field inthe CAPREG register (Device 0, Offset E4h) is RO at 00h. This enables internal graphicscapability.0 = Enable. Internal Graphics is enabled (default)224 Intel ® 82865G/82865GV GMCH Datasheet
Intel ® 82865GV GMCHGMCHCFG—GMCH Configuration Register (Device 0)Address OffsetDefault ValueAccessSize:C6–C7h0000hR/W, RO16 bitsBits3DescriptionAGP Mode (AGP/DVO#)—RO. This bit reflects the ADD_DETECT strap value. This strap bitdetermines the function of the AGP I/O signal.0 = 2xDVO1 = no DVO mode, internal graphics only.When the strap is sampled low, this bit is 0 and Intel ® DVO mode is selected. When the strap issampled high, this bit is 1 and DVO mode is not selected, and the internal graphics device isrunning.Note that when this bit is set to 0 (DVO mode), Device 1 is disabled (configuration cycles fallthroughto the hub interface) and the Next Pointer field in CAPREG will be hardwired to 0s.ERRSTS—Error Status Register (Device 0)Address OffsetDefault ValueAccessSize:C8–C9h0000hR/WC16 bitsBitsDescription4:0 Intel ReservedERRCMD—Error Command Register (Device 0)Address OffsetDefault ValueAccessSize:CA–CBh0000hRO, R/W16 bitsBitsDescription4:0 Intel ReservedIntel ® 82865G/82865GV GMCH Datasheet 225
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Intel ® 865G/865GV ChipsetDatashee
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Contents1 Introduction.............
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3.8 PCI-to-CSA Bridge Registers (De
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5.5.3 Synchronous Display .........
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Tables1 General Terminology .......
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Introduction1.4 Intel ® 82865G GMC
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Introduction1.4.7 Display Interface
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Signal Description2.1 Host Interfac
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Signal DescriptionSignal Name Type
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Signal Description2.2.2 DDR SDRAM C
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Signal Description2.5 AGP Interface
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Signal Description2.5.4 AGP Strobes
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Signal DescriptionSignal Name Type
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Signal Description2.5.7 Intel ® DV
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Signal Description2.7 Clocks, Reset
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Signal Description2.10 GMCH Sequenc
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Signal Description2.12 Full and War
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Register DescriptionTermReservedReg
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Register Description3.3 Routing Con
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Register DescriptionIf the Bus Numb
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Register Description3.4.2 CONFIG_DA
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Register DescriptionTable 6.DRAM Co
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Register Description3.5.3 PCICMD—
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Register Description3.5.5 RID—Rev
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Register Description3.5.10 APBASE
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Register Description3.5.14 AGPM—A
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Register DescriptionNotes on Pre-Al
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Register Description3.5.17 FPLLCONT
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Register DescriptionAs an example,
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Register Description3.5.20 SMRAM—
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Register Description3.5.22 ACAPID
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Register Description3.5.24 AGPCMD
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Register Description3.5.26 APSIZE
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Register Description3.5.29 LPTT—A
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Register Description3.5.31 GMCHCFG
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Register Description3.5.32 ERRSTS
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Register Description3.5.34 SKPD—S
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Register Description3.6.1 VID1—Ve
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Register Description3.6.4 PCISTS1
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Register Description3.6.8 MLT1—Ma
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Register Description3.6.14 IOBASE1
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Register Description3.6.17 MBASE1
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Register Description3.6.22 ERRCMD1
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Register Description3.7.6 CC—Clas
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Register Description3.7.11 MMADR—
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Register Description3.7.16 CAPPOINT
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Register Description3.7.22 PMCAP—
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Register Description3.8 PCI-to-CSA
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Register Description3.8.3 PCICMD3
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Register Description3.8.5 RID3—Re
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Register Description3.8.11 SBUSN3
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Register Description3.8.15 SSTS3—
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Register Description3.8.17 MLIMIT3
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Register Description3.8.20 BCTRL3
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Register Description3.9 Overflow Co
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Register Description3.9.4 PCISTS6
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Register Description3.9.9 BAR6—Me
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Register DescriptionThe remaining 7
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Register Description3.10.3 DRT—DR
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Register DescriptionBit6:4Descripti
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System Address MapSystem Address Ma
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System Address Map4.2 Compatibility
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System Address Map4.3 Extended Memo
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System Address MapPCI Memory Addres
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Functional DescriptionFunctional De
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Functional Description5.2 System Me
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Functional Description5.2.2.1 Dynam
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Functional DescriptionTable 21. DRA
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Functional DescriptionTable 23. DRA
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Functional Description5.2.6 Configu
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Functional Description5.3.1 GMCH AG
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Functional Descriptiondown controll
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Functional Description5.3.6 Support
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Functional Description5.4.1 3D Engi
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Functional DescriptionTexture Forma
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Functional DescriptionTexture Map B
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Functional DescriptionDepth BufferT
Page 173 and 174: Functional Description5.4.3 Video E
Page 175 and 176: Functional Description5.4.5 PipesSc
Page 177 and 178: Functional DescriptionIntegrated RA
Page 179 and 180: Functional DescriptionDirect YUV fr
Page 181 and 182: Functional Description• System—
Page 183 and 184: Functional Description5.8 ClockingT
Page 185 and 186: Electrical CharacteristicsElectrica
Page 187 and 188: Electrical CharacteristicsTable 36.
Page 189 and 190: Electrical Characteristics6.5 DC Pa
Page 195 and 196: Electrical Characteristics6.6.3 DAC
Page 197 and 198: Ballout and Package InformationBall
Page 199 and 200: Ballout and Package InformationFigu
Page 201 and 202: Ballout and Package InformationTabl
Page 209 and 210: Ballout and Package Information7.2
Page 211 and 212: TestabilityTestability 8In the GMCH
Page 213 and 214: Testability8.2 XOR Chain Definition
Page 215 and 216: TestabilityTable 45. XOR Chain 1 (3
Page 221 and 222: Intel ® 82865GV GMCHIntel ® 82865
Page 223: Intel ® 82865GV GMCH9.3 Intel ® 8
Page 227 and 228: Intel ® 82865GV GMCH BalloutIntel
Page 229 and 230: Intel ® 82865GV GMCH BalloutFigure
Page 231 and 232: Intel ® 82865GV GMCH BalloutTable
Page 241 and 242: Intel ® 82865GV GMCH TestabilityIn
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IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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