Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.5.4 PCISTS—PCI Status Register (Device 0)Address Offset: 06–07hDefault Value: 0090hAccess:RO, R/WCSize:16 bitsPCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCIinterface. Since GMCH Device 0 does not physically reside on PCI_A, many of the bits are notimplemented.BitDescriptions15 Detected Parity Error (DPE)—RO. Hardwired to 0.1413121110:98Signaled System Error (SSE)—R/WC.0 = Software sets this bit to 0 by writing a 1 to it.1 = GMCH Device 0 generated a SERR message over HI for any enabled Device 0 errorcondition. Device 0 error conditions are enabled in the PCICMD and ERRCMD registers.Device 0 error flags are read/reset from the PCISTS or ERRSTS registers.Received Master Abort Status (RMAS)—R/WC.0 = Software sets this bit to 0 by writing a 1 to it.1 = GMCH generated a HI request that receives a Master Abort completion packet or MasterAbort Special Cycle.Received Target Abort Status (RTAS)—R/WC.0 = Software sets this bit to 0 by writing a 1 to it.1 = GMCH generated a HI request that receives a Target Abort completion packet or Target AbortSpecial Cycle.Signaled Target Abort Status (STAS)—RO. Hardwired to 0. The GMCH will not generate aTarget Abort HI completion packet or Special Cycle.DEVSEL Timing (DEVT)—RO. Hardwired to 00. Device 0 does not physically connect to PCI_A.These bits are set to 00 (fast decode) so that optimum DEVSEL timing for PCI_A is not limited bythe GMCH.Master Data Parity Error Detected (DPD)—RO. Hardwired to 0. PERR signaling and messagingare not implemented by the GMCH.Fast Back-to-Back (FB2B)—RO. Hardwired to 1. Device 0 does not physically connect to PCI_A.7 This bit is set to 1 (indicating fast back-to-back capability) so that the optimum setting for PCI_A isnot limited by the GMCH.6:5 Reserved.Capability List (CLIST)—RO. Hardwired to 1. A 1 indicates to the configuration software that thisdevice/function implements a list of new capabilities. A list of new capabilities is accessed via4 register CAPPTR at configuration address offset 34h. Register CAPPTR contains an offsetpointing to the start address within configuration space of this device where the AGP Capabilitystandard register resides.3:0 Reserved.Intel ® 82865G/82865GV GMCH Datasheet 59