Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Functional DescriptionFunctional Description 5This chapter describes the GMCH interfaces and functional units including the processor systembus interface, the AGP interface, system memory controller, integrated graphics device, DVOinterfaces, display interfaces, power management, and clocking.5.1 Processor Front Side Bus (FSB)The GMCH supports a single Pentium 4 processor with 512-KB L2 cache on 0.13 micron processin a 478-pin package or the Pentium 4 processor on 90 nm process. The GMCH supports FSBfrequencies of 400 MHz, 533 MHz, and 800 MHz using a scalable FSB VTT voltage and on-dietermination. It supports 32-bit host addressing, decoding up to 4 GB of the processor’s memoryaddress space. Host-initiated I/O cycles are decoded to AGP/PCI_B, Hub Interface, or the GMCHconfiguration space. Host-initiated memory cycles are decoded to AGP/PCI_B, Hub Interface orsystem memory. All memory accesses from the host interface that hit the graphics aperture aretranslated using an AGP address translation table. AGP/PCI_B device accesses to non-cacheablesystem memory are not snooped on the host bus. Memory accesses initiated from AGP/PCI_Busing PCI semantics and from the hub interface to system memory will be snooped on the host bus.The GMCH supports the Pentium 4 processor subset of the Enhanced Mode Scalable Bus. Thecache line size is 64 bytes. Source synchronous transfer is used for the address and data signals. At100/133/200 MHz bus clock the address signals are double pumped to run at 200/266/400 MHzand a new address can be generated every other bus clock. At 100/133/200 MHz bus clock the datasignals are quad pumped to run at 400/533/800 MHz and an entire 64-B cache line can betransferred in two bus clocks.The GMCH integrates AGTL+ termination resistors on die. The GMCH has an IOQ depth of 12.The GMCH supports one outstanding deferred transaction on the FSB.5.1.1 FSB Dynamic Bus InversionThe GMCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data fromthe processor. DBI limits the number of data signals that are driven to a low voltage on each quadpumped data phase. This decreases the worst-case power consumption of the GMCH. DINV[3:0]#indicate if the corresponding 16 bits of data are inverted on the bus for each quad pumped dataphase:DINV[3:0]#DINV0#DINV1#DINV2#DINV3#Data BitsHD[15:0]#HD[31:16]#HD[47:32]#HD[63:48]#Intel ® 82865G/82865GV GMCH Datasheet 147