Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.6 PCI-to-AGP Bridge Configuration Register(Device 1)This section contains the PCI-to-AGP bridge PCI configuration registers listed in order ofascending offset address. The register address map is shown in Table 8.Table 8. PCI-to-AGP Bridge PCI Configuration Register Address Map (Device 1)AddressOffsetRegisterSymbolRegister Name Default Value Access00–01h VID1 Vendor Identification 8086h RO02–03h DID1 Device Identification 2571h RO04–05h PCICMD1 PCI Command 0000h RO, R/W06–07h PCISTS1 PCI Status 00A0h RO, R/WC08h RID1 Revision IdentificationSee registerdescriptionRO09h — Reserved — —0Ah SUBC1 Sub-Class Code 04h RO0Bh BCC1 Base Class Code 06h RO0Ch — Reserved — —0Dh MLT1 Master Latency Timer 00h RO, R/W0Eh HDR1 Header Type 01h RO0F–17h — Reserved — —18h PBUSN1 Primary Bus Number 00h RO19h SBUSN1 Secondary Bus Number 00h R/W1Ah SUBUSN1 Subordinate Bus Number 00h R/W1Bh SMLT1 Secondary Bus Master Latency Timer 00h RO, R/W1Ch IOBASE1 I/O Base Address F0h RO, R/W1Dh IOLIMIT1 I/O Limit Address 00h RO, R/W1E–1Fh SSTS1 Secondary Status 02A0h RO, R/WC20–21h MBASE1 Memory Base Address FFF0h RO, R/W22–23h MLIMIT1 Memory Limit Address 0000h RO, R/W24–25h PMBASE1 Prefetchable Memory Base Address FFF0h RO, R/W26–27h PMLIMIT1 Prefetchable Memory Limit Address 0000h RO, R/W28–3Dh — Reserved — —3Eh BCTRL1 Bridge Control 00h RO, R/W3Fh — Reserved — —40h ERRCMD1 Error Command 00h RO, R/W41–FFh — Reserved — —Intel ® 82865G/82865GV GMCH Datasheet 87