Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.8.21 ERRCMD3—Error Command Register (Device 3)Address Offset:Default Value:Access:Size:40h00hR/W, RO8 bitsBitDescription7:1 Reserved.0SERR on Receiving Target Abort (SERTA)—R/W.0 = The GMCH does not assert a SERR message upon receipt of a target abort on CSA.1 = The GMCH generates a SERR message over CSA upon receiving a target abort on CSA.SERR messaging for Device 3 is globally enabled in the PCICMD3 register.3.8.22 CSACNTRL—CSA Control Register (Device 3)Address Offset: 50–53hDefault Value: 0E042802hAccess:R/W, ROSize:32 bitsBitDescription31:29First Subordinate CSA (CSA_SUB_FIRST)—R/W. This field stores the lowest subordinate CI hubnumber.28 Reserved.27:25Last Subordinate CSA (CSA_SUB_LAST)—R/W. This field stores the highest subordinate CSAhub number.24:16 Reserved.CSA Width (CSA_WIDTH)—R/W. This field describes the used width of the data bus.00 = 8 bit15:14 01 = Reserved10 = Reserved11 = Reserved13:0 Intel Reserved.126 Intel ® 82865G/82865GV GMCH Datasheet