IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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Ballout and Package InformationFigure 19. Intel ® 82865G GMCH Package Dimensions (Bottom View)0.7668Detail A0.76681.0 mmMin.Detail B0.4529Detail BPin A1Detail ABGA Land; 932 ballsϕ 0.600 (932 places)0.57 ±0.10.7 ±0.050.7 ±0.050.203LA B S0.071 L ACS0.57 ±0.1ϕ 0.63 ±0.0250.7 ±0.05ϕ 0.47 ±0.04Units = Millimeters865_Pkg_Bottom_rev2210 Intel ® 82865G/82865GV GMCH Datasheet
TestabilityTestability 8In the GMCH, testability for Automated Test Equipment (ATE) board level testing has beenimplemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pinconnected to it.8.1 XOR Test Mode InitializationXOR test mode can be entered by driving GSBA6#, GSBA7#, TESTIN#, PWROK low, andRSTIN# low, then driving PWROK high, then RSTIN# high. XOR test mode via TESTIN# doesnot require a clock. But toggling of HCLKP and HCLKN as shown in Figure 20 is required fordeterministic XOR operation when in AGP 2.0 mode. If the component is in AGP 3.0 mode,GSBA6#, GSBA7#, and GC#/BE1 must be driven high.Figure 20. XOR Toggling of HCLKP and HCLKNPWROK1 msTESTIN#GSBA6GFRAME#RSTIN#GCLKINHCLKPHCLKNDREFCLKPin testing will not start until RSTIN# is deasserted. Figure 21 shows chains that are testedsequentially. Note that for the GMCH, sequential testing is not required. All chains can be tested inparallel for test time reduction.Intel ® 82865G/82865GV GMCH Datasheet 211
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Intel ® 865G/865GV ChipsetDatashee
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Contents1 Introduction.............
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3.8 PCI-to-CSA Bridge Registers (De
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5.5.3 Synchronous Display .........
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Tables1 General Terminology .......
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Introduction1.4 Intel ® 82865G GMC
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Introduction1.4.7 Display Interface
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Signal Description2.1 Host Interfac
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Signal DescriptionSignal Name Type
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Signal Description2.2.2 DDR SDRAM C
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Signal Description2.5 AGP Interface
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Signal Description2.5.4 AGP Strobes
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Signal DescriptionSignal Name Type
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Signal Description2.5.7 Intel ® DV
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Signal Description2.7 Clocks, Reset
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Signal Description2.10 GMCH Sequenc
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Signal Description2.12 Full and War
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Register DescriptionTermReservedReg
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Register Description3.3 Routing Con
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Register DescriptionIf the Bus Numb
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Register Description3.4.2 CONFIG_DA
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Register DescriptionTable 6.DRAM Co
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Register Description3.5.3 PCICMD—
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Register Description3.5.5 RID—Rev
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Register Description3.5.10 APBASE
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Register Description3.5.14 AGPM—A
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Register DescriptionNotes on Pre-Al
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Register Description3.5.17 FPLLCONT
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Register DescriptionAs an example,
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Register Description3.5.20 SMRAM—
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Register Description3.5.22 ACAPID
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Register Description3.5.24 AGPCMD
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Register Description3.5.26 APSIZE
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Register Description3.5.29 LPTT—A
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Register Description3.5.31 GMCHCFG
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Register Description3.5.32 ERRSTS
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Register Description3.5.34 SKPD—S
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Register Description3.6.1 VID1—Ve
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Register Description3.6.4 PCISTS1
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Register Description3.6.8 MLT1—Ma
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Register Description3.6.14 IOBASE1
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Register Description3.6.17 MBASE1
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Register Description3.6.22 ERRCMD1
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Register Description3.7.6 CC—Clas
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Register Description3.7.11 MMADR—
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Register Description3.7.16 CAPPOINT
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Register Description3.7.22 PMCAP—
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Register Description3.8 PCI-to-CSA
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Register Description3.8.3 PCICMD3
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Register Description3.8.5 RID3—Re
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Register Description3.8.11 SBUSN3
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Register Description3.8.15 SSTS3—
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Register Description3.8.17 MLIMIT3
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Register Description3.8.20 BCTRL3
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Register Description3.9 Overflow Co
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Register Description3.9.4 PCISTS6
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Register Description3.9.9 BAR6—Me
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Register DescriptionThe remaining 7
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Register Description3.10.3 DRT—DR
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Register DescriptionBit6:4Descripti
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System Address MapSystem Address Ma
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System Address Map4.2 Compatibility
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System Address Map4.3 Extended Memo
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System Address MapPCI Memory Addres
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Functional DescriptionFunctional De
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Functional Description5.2 System Me
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Functional Description5.2.2.1 Dynam
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Functional DescriptionTable 21. DRA
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Functional DescriptionTable 23. DRA
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Functional Description5.2.6 Configu
Page 159 and 160: Functional Description5.3.1 GMCH AG
Page 161 and 162: Functional Descriptiondown controll
Page 163 and 164: Functional Description5.3.6 Support
Page 165 and 166: Functional Description5.4.1 3D Engi
Page 167 and 168: Functional DescriptionTexture Forma
Page 169 and 170: Functional DescriptionTexture Map B
Page 171 and 172: Functional DescriptionDepth BufferT
Page 173 and 174: Functional Description5.4.3 Video E
Page 175 and 176: Functional Description5.4.5 PipesSc
Page 177 and 178: Functional DescriptionIntegrated RA
Page 179 and 180: Functional DescriptionDirect YUV fr
Page 181 and 182: Functional Description• System—
Page 183 and 184: Functional Description5.8 ClockingT
Page 185 and 186: Electrical CharacteristicsElectrica
Page 187 and 188: Electrical CharacteristicsTable 36.
Page 189 and 190: Electrical Characteristics6.5 DC Pa
Page 195 and 196: Electrical Characteristics6.6.3 DAC
Page 197 and 198: Ballout and Package InformationBall
Page 199 and 200: Ballout and Package InformationFigu
Page 201 and 202: Ballout and Package InformationTabl
Page 209: Ballout and Package Information7.2
Page 213 and 214: Testability8.2 XOR Chain Definition
Page 215 and 216: TestabilityTable 45. XOR Chain 1 (3
Page 221 and 222: Intel ® 82865GV GMCHIntel ® 82865
Page 223 and 224: Intel ® 82865GV GMCH9.3 Intel ® 8
Page 225 and 226: Intel ® 82865GV GMCHGMCHCFG—GMCH
Page 227 and 228: Intel ® 82865GV GMCH BalloutIntel
Page 229 and 230: Intel ® 82865GV GMCH BalloutFigure
Page 231 and 232: Intel ® 82865GV GMCH BalloutTable
Page 241 and 242: Intel ® 82865GV GMCH TestabilityIn
Page 243 and 244: Intel ® 82865GV GMCH Testability11
Page 245 and 246: Intel ® 82865GV GMCH TestabilityTa
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IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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