Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Intel ® 82865GV GMCHATTBASE — Aperture Translation Table Register (Device 0)Address OffsetSize:B8–BBh32 bitsAMTT — AGP MTT Control Register (Device 0)Address OffsetSize:BC–BFh8 bitsLPTT — AGP Low Priority Transaction Timer Register (Device 0)Address OffsetSize:BDh8 bits9.3.1.2 Device 0 Register Bit DifferencesThe registers described in this section are in both the 82865G and 82865GV. However, some of theregister bits have different functions/operations between the two components. Only the bits that aredifferent are shown in this section. The remaining register bits are the same for both the 82865Gand 82865GV and are described in Chapter 3.GC—Graphics Control Register (Device 0)Address OffsetDefault ValueAccessSize:52h0000_0000bRO, R/W. R/W/L8 bitsBitsDescription3Integrated Graphics Disable (IGDIS) — RO. The GMCH’s Device 1 is disabled such that allconfiguration cycles to Device 1 flow through to the hub interface. Also, the Next_Pointer field inthe CAPREG register (Device 0, Offset E4h) is RO at 00h. This enables internal graphicscapability.0 = Enable. Internal Graphics is enabled (default)224 Intel ® 82865G/82865GV GMCH Datasheet