IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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Signal Description2.12 Full and Warm Reset StatesFigure 4. Full and Warm Reset WaveformsIntel ® ICH5 PowerICH5 PWROK InICH5 PCIRST# OutGMCH RSTIN# InGMCH CPURST# OutWrite to1 ms Min 1 ms minCF9h1 ms1 msGMCH PowerGMCH PWROK InGMCH Reset StateUnknown Full Reset Warm Reset Running Warm Reset RunningAll register bits assume their default values during full reset. PCIRST# resets all internal flip flopsand state machines (except for a few configuration register bits). A full reset occurs whenPCIRST# (GMCH RSTIN#) is asserted and PWROK is deasserted. A warm reset occurs whenPCIRST# (GMCH RSTIN#) is asserted and PWROK is also asserted. The following tabledescribes the reset states.Reset State RSTIN# PWROKFull Reset L LWarm Reset L HDoes Not Occur H LNormal Operation H H46 Intel ® 82865G/82865GV GMCH Datasheet
Register DescriptionRegister Description 3The GMCH contains two sets of software accessible registers, accessed via the host processor I/Oaddress space:• Control registers that are I/O mapped into the processor I/O space control access to PCI andAGP configuration space.• Internal configuration registers residing within the GMCH are partitioned into three logicaldevice register rests (“logical” since they reside within a single physical device). The firstregister set is dedicated to Host-Hub Interface functionality (controls PCI bus #0 operationsincluding DRAM configuration, other chipset operating parameters, and optional features).The second register block is dedicated to Host-AGP/PCI_B Bridge functions (controls AGP/PCI_B interface configurations and operating parameters). The third register block isdedicated to the Integrated Graphics Device (IGD).This configuration scheme is necessary to accommodate the existing and future softwareconfiguration model supported by Microsoft where the host bridge functionality will be supportedand controlled via dedicated and specific driver and virtual PCI-to-PCI bridge functionality will besupported via standard PCI bus enumeration configuration software. The term “virtual” is used todesignate that no real physical embodiment of the PCI-to-PCI bridge functionality exists within theGMCH, but that GMCH’s internal configuration register sets are organized in this particularmanner to create that impression to the standard configuration software.The GMCH supports PCI configuration space accesses using the mechanism denoted asConfiguration Mechanism 1 in the PCI specification. The GMCH internal registers (both I/Omapped and configuration registers) are accessible by the host processor. The registers can beaccessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with the exception ofCONFIG_ADDRESS which can only be accessed as a DWord. All multi-byte numeric fields use“little-endian” ordering (i.e., lower addresses contain the least significant parts of the field).3.1 Register TerminologyTermROR/WR/W/LR/WCR/WOLReserved BitsDescriptionRead Only. If a register is read only, writes to this register have no effect.Read/Write. A register with this attribute can be read and written.Read/Write/Lock. A register with this attribute can be read, written, and Locked.Read/Write Clear. A register bit with this attribute can be read and written. However, awrite of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.Read/Write Once. A register bit with this attribute can be written to only once after powerup. After the first write, the bit becomes read only.Lock. A register bit with this attribute becomes Read Only after a lock bit is set.Some of the GMCH registers described in this section contain reserved bits. These bitsare labeled “Reserved”. Software must deal correctly with fields that are reserved. Onreads, software must use appropriate masks to extract the defined bits and not rely onreserved bits being any particular value. On writes, software must ensure that the valuesof reserved bit positions are preserved. That is, the values of reserved bit positions mustfirst be read, merged with the new values for other bit positions and then written back.Note that software does not need to perform a read-merge-write operation for theConfiguration Address (CONFIG_ADDRESS) register.Intel ® 82865G/82865GV GMCH Datasheet 47
Page 1 and 2: Intel ® 865G/865GV ChipsetDatashee
Page 3: Contents1 Introduction.............
Page 6 and 7: 3.8 PCI-to-CSA Bridge Registers (De
Page 8 and 9: 5.5.3 Synchronous Display .........
Page 10 and 11: Tables1 General Terminology .......
Page 14: This page is intentionally left bla
Page 20 and 21: Introduction1.4 Intel ® 82865G GMC
Page 24: Introduction1.4.7 Display Interface
Page 27 and 28: Signal Description2.1 Host Interfac
Page 29 and 30: Signal DescriptionSignal Name Type
Page 31 and 32: Signal Description2.2.2 DDR SDRAM C
Page 33 and 34: Signal Description2.5 AGP Interface
Page 35 and 36: Signal Description2.5.4 AGP Strobes
Page 37 and 38: Signal DescriptionSignal Name Type
Page 39 and 40: Signal Description2.5.7 Intel ® DV
Page 41 and 42: Signal Description2.7 Clocks, Reset
Page 44 and 45: Signal Description2.10 GMCH Sequenc
Page 48 and 49: Register DescriptionTermReservedReg
Page 50 and 51: Register Description3.3 Routing Con
Page 52 and 53: Register DescriptionIf the Bus Numb
Page 54 and 55: Register Description3.4.2 CONFIG_DA
Page 56 and 57: Register DescriptionTable 6.DRAM Co
Page 58 and 59: Register Description3.5.3 PCICMD—
Page 60 and 61: Register Description3.5.5 RID—Rev
Page 62 and 63: Register Description3.5.10 APBASE
Page 64 and 65: Register Description3.5.14 AGPM—A
Page 66 and 67: Register DescriptionNotes on Pre-Al
Page 68 and 69: Register Description3.5.17 FPLLCONT
Page 70 and 71: Register DescriptionAs an example,
Page 72 and 73: Register Description3.5.20 SMRAM—
Page 74 and 75: Register Description3.5.22 ACAPID
Page 76 and 77: Register Description3.5.24 AGPCMD
Page 78 and 79: Register Description3.5.26 APSIZE
Page 80 and 81: Register Description3.5.29 LPTT—A
Page 82 and 83: Register Description3.5.31 GMCHCFG
Page 84 and 85: Register Description3.5.32 ERRSTS
Page 86 and 87: Register Description3.5.34 SKPD—S
Page 88 and 89: Register Description3.6.1 VID1—Ve
Page 90 and 91: Register Description3.6.4 PCISTS1
Page 92 and 93: Register Description3.6.8 MLT1—Ma
Page 94 and 95: Register Description3.6.14 IOBASE1
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Register Description3.6.17 MBASE1
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Register Description3.6.22 ERRCMD1
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Register Description3.7.6 CC—Clas
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Register Description3.7.11 MMADR—
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Register Description3.7.16 CAPPOINT
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Register Description3.7.22 PMCAP—
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Register Description3.8 PCI-to-CSA
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Register Description3.8.3 PCICMD3
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Register Description3.8.5 RID3—Re
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Register Description3.8.11 SBUSN3
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Register Description3.8.15 SSTS3—
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Register Description3.8.17 MLIMIT3
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Register Description3.8.20 BCTRL3
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Register Description3.9 Overflow Co
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Register Description3.9.4 PCISTS6
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Register Description3.9.9 BAR6—Me
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Register DescriptionThe remaining 7
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Register Description3.10.3 DRT—DR
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Register DescriptionBit6:4Descripti
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System Address MapSystem Address Ma
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System Address Map4.2 Compatibility
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System Address Map4.3 Extended Memo
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System Address MapPCI Memory Addres
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Functional DescriptionFunctional De
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Functional Description5.2 System Me
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Functional Description5.2.2.1 Dynam
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Functional DescriptionTable 21. DRA
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Functional DescriptionTable 23. DRA
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Functional Description5.2.6 Configu
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Functional Description5.3.1 GMCH AG
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Functional Descriptiondown controll
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Functional Description5.3.6 Support
Page 165 and 166:
Functional Description5.4.1 3D Engi
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Functional DescriptionTexture Forma
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Functional DescriptionTexture Map B
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Functional DescriptionDepth BufferT
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Functional Description5.4.3 Video E
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Functional Description5.4.5 PipesSc
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Functional DescriptionIntegrated RA
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Functional DescriptionDirect YUV fr
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Functional Description• System—
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Functional Description5.8 ClockingT
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Electrical CharacteristicsElectrica
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Electrical CharacteristicsTable 36.
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Electrical Characteristics6.5 DC Pa
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Electrical Characteristics6.6.3 DAC
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Ballout and Package InformationBall
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Ballout and Package InformationFigu
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Ballout and Package InformationTabl
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Ballout and Package Information7.2
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TestabilityTestability 8In the GMCH
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Testability8.2 XOR Chain Definition
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TestabilityTable 45. XOR Chain 1 (3
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Intel ® 82865GV GMCHIntel ® 82865
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Intel ® 82865GV GMCH9.3 Intel ® 8
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Intel ® 82865GV GMCHGMCHCFG—GMCH
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Intel ® 82865GV GMCH BalloutIntel
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Intel ® 82865GV GMCH BalloutFigure
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Intel ® 82865GV GMCH BalloutTable
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Intel ® 82865GV GMCH TestabilityIn
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Intel ® 82865GV GMCH Testability11
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Intel ® 82865GV GMCH TestabilityTa
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IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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