Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Functional Description5.3.6 Support for PCI-66 DevicesThe GMCH’s AGP interface may be used as a PCI-66 MHz interface with the followingrestrictions:1. Support for 1.5 V operation only.2. Support for only one device. The GMCH does not provide arbitration or electrical support formore than one PCI-66 device.3. The PCI-66 device must meet the AGP 2.0 electrical specification.4. The GMCH does not provide full PCI-to-PCI bridge support between AGP/PCI and hubinterface. Traffic between AGP and hub interface is limited to hub interface-to-AGP memorywrites.5. LOCK# signal is not present. Neither inbound nor outbound locks are supported.6. SERR# / PERR# signals are not present.7. 16-clock Subsequent Data Latency timer (instead of 8).5.3.7 8X AGP ProtocolThe GMCH supports 1X and 4X AGP operation in 2.0 mode, and 4X and 8X in 3.0 mode. Bit 3 ofthe AGP status register is set to 0 in AGP 2.0 mode, and 1 in APG 3.0 mode. The GMCH indicatesthat it supports 8X data transfers in AGP 3.0 mode through RATE[1] of the AGP status register.When DATA_RATE[1] of the AGP Command Register is set to 1 during system initialization, theGMCH will perform AGP read and write data transactions using 8X protocol. This bit is set onceduring initialization and the data transfer rate cannot be changed dynamically.The 8X data transfer protocol provides 2.1 GB/s transfer rates. In 8X mode, 32 bytes of data aretransferred during each 66 MHz clock period. The minimum throttleable block size remains four,66 MHz clocks, which means 128 bytes of data is transferred per block.5.3.7.1 Fast WritesThe Fast Write (FW) transaction is from the core logic to the AGP master acting as a PCI target.This type of access is required to pass data/control directly to the AGP master instead of placingthe data into main memory and then having the AGP master read the data. For 1X transactions, theprotocol simply follows the PCI bus specification. However, for higher speed transactions (4X or8X), FW transactions follow a combination for PCI and AGP bus protocols for data movement.The GMCH only supports the AGP 1.5 V connector, which permits a 1.5 V AGP add-in card to besupported by the system.5.3.7.2 PCI Semantic Transactions on AGPThe GMCH accepts and generates PCI semantic transactions on the AGP bus. The GMCHguarantees that PCI semantic accesses to SDRAM are kept coherent with the processor caches bygenerating snoops to the processor bus.Intel ® 82865G/82865GV GMCH Datasheet 163