Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.5.24 AGPCMD—AGP Command Register (Device 0)Address Offset:Default Value:Access:Size:A8–ABh00000000h in AGP 2.0 mode00000A00h in AGP 3.0 modeRO, R/W32 bitsThis register provides control of the AGP operational parameters.BitDescriptions31:13 Reserved.12:109PCAL_Cycle—R/W. This filed is programmed with the period for GMCH-initiated bus cycle forcalibrating I/O buffers for both master and target. This value is updated with the smaller of thevalue in CAL_CYCLE from Master’s and Target’s AGPSTAT.CAL_CYCLE. PCAL_CYCLE is set to111 by software only if both the Target and Master have AGPSTAT.CAL_CYCLE = 111.000 = 4 ms001 = 16 ms010 = 64 ms (Default).011 = 256 ms100–110 = Reserved111 = Calibration Cycle Not NeededSide Band AddressingEnable (SBAEN)—R/W. This bit is ignored in AGP 3.0 mode to allowlegacy 2.0 software to work. (When AGP 3.0 is detected, sideband addressing mechanism isautomatically enabled by the hardware.)0 = Disable.1 = Enable. Side band addressing mechanism is enabled.AGP Enable (AGPEN)—R/W.0 = Disable. GMCH ignores all AGP operations, including the sync cycle. Any AGP operationsreceived while this bit is set to 1 will be serviced, even if this bit is reset to 0. If this bit8 transitions from 1 to 0 on a clock edge in the middle of an SBA command being delivered in1X mode, the command will be issued.1 = Enable. GMCH responds to AGP operations delivered via PIPE#, or to operations deliveredvia SBA if the AGP Side Band Enable bit is also set to 1.7:6 Reserved.5Greater Than Four Gigabyte Enable (GT4GIGE)—RO. Hardwired to 0 indicating that the GMCH,as an AGP target, does not support addressing greater than 4 GB.Fast Write Enable (FWEN)—R/W.0 = Disable. When this bit is cleared, or when the data rate bits are set to 1X mode, the memory4 write transactions from the GMCH to the AGP master use standard PCI protocol.1 = Enable. The GMCH uses the Fast Write protocol for memory write transactions from theGMCH to the AGP master. Fast Writes will occur at the data transfer rate selected by the datarate bits (2:0) in this register.3 Reserved.2:0Data Rate Enable (DRATE)—R/W. The setting of these bits determines the AGP data transferrate. One (and only one) bit in this field must be set to indicate the desired data transfer rate. Thesame bit must be set on both master and target.AGP 2.0001= 1X Transfer Mode (for AGP 2.0 signaling)010= 2X Transfer Mode (NOT SUPPORTED)100= 4X Transfer Mode (for AGP 2.0 signaling)AGP 3.0001= 4X transfer mode (for AGP 3.0 signaling)010= 8X Transfer mode (for AGP 3.0 signaling)100= Reserved76 Intel ® 82865G/82865GV GMCH Datasheet