Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Contents1 Introduction...........................................................................................................151.1 Terminology ...................................................................................................161.2 Related Documents .......................................................................................171.3 Intel ® 865G Chipset System Overview ..........................................................181.4 Intel ® 82865G GMCH Overview ....................................................................201.4.1 Host Interface....................................................................................201.4.2 System Memory Interface .................................................................201.4.3 Hub Interface ....................................................................................211.4.4 Communications Streaming Architecture (CSA) Interface................211.4.5 Multiplexed AGP and Intel ® DVO Interface.......................................211.4.6 Graphics Overview............................................................................221.4.7 Display Interface ...............................................................................241.5 Clock Ratios...................................................................................................242 Signal Description ..............................................................................................252.1 Host Interface Signals....................................................................................272.2 Memory Interface ...........................................................................................302.2.1 DDR SDRAM Channel A ..................................................................302.2.2 DDR SDRAM Channel B ..................................................................312.3 Hub Interface .................................................................................................322.4 Communication Streaming Architecture (CSA) Interface...............................322.5 AGP Interface ................................................................................................332.5.1 AGP Addressing Signals...................................................................332.5.2 AGP Flow Control Signals ................................................................342.5.3 AGP Status Signals ..........................................................................342.5.4 AGP Strobes .....................................................................................352.5.5 PCI Signals–AGP Semantics............................................................362.5.5.1 PCI Pins during PCI Transactions on AGP Interface ........372.5.6 Multiplexed Intel ® DVOs on AGP......................................................372.5.7 Intel ® DVO-to-AGP Pin Mapping.......................................................392.6 Analog Display Interface ................................................................................402.7 Clocks, Reset, and Miscellaneous Signals ....................................................412.8 RCOMP, VREF, VSWING Signals.................................................................422.9 Power and Ground Signals ............................................................................432.10 GMCH Sequencing Requirements.................................................................442.11 Signals Used As Straps .................................................................................452.11.1 Functional Straps ..............................................................................452.11.2 Strap Input Signals............................................................................452.12 Full and Warm Reset States ..........................................................................463 Register Description..........................................................................................473.1 Register Terminology.....................................................................................473.2 Platform Configuration Structure....................................................................483.3 Routing Configuration Accesses....................................................................503.3.1 Standard PCI Bus Configuration Mechanism ...................................503.3.2 PCI Bus #0 Configuration Mechanism ..............................................503.3.3 Primary PCI and Downstream Configuration Mechanism.................503.3.4 AGP/PCI_B Bus Configuration Mechanism ......................................51Intel ® 82865G/82865GV GMCH Datasheet 3