Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.5.21 ESMRAMC—Extended System Management RAM Control(Device 0)Address Offset:Default Value:Access:Size:9Eh38hR/W, R/WC, RO, Lock8 bitsThe Extended SMRAM register controls the configuration of Extended SMRAM space. TheExtended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memoryspace that is above 1 MB.Bit76DescriptionsEnable High SMRAM (H_SMRAME)—R/W/L. This bit controls the SMM memory space location(i.e., above 1 MB or below 1 MB). When G_SMRAME is 1 and H_SMRAME (this bit) is set to 1, thehigh SMRAM memory space is enabled. SMRAM accesses within the range 0FEDA0000h to0FEDBFFFFh are remapped to SDRAM addresses within the range 000A0000h to 000BFFFFh.Once D_LCK has been set, this bit becomes read only.Invalid SMRAM Access (E_SMERR)—R/WC. This bit is set when the processor has accessedthe defined memory ranges in Extended SMRAM (High Memory and T-segment) while not in SMMspace and with the D-OPEN bit = 0. It is software’s responsibility to clear this bit.NOTE: Software must write a 1 to this bit to clear it.5 SMRAM Cacheable (SM_CACHE)—RO. Hardwired to 1.4 L1 Cache Enable for SMRAM (SM_L1)—RO. Hardwired to 1.3 L2 Cache Enable for SMRAM (SM_L2)—RO. Hardwired to 1.2:10TSEG Size (TSEG_SZ)—R/W. This field selects the size of the TSEG memory block, if enabled.Memory from the top of SDRAM space (TOUD +TSEG_SZ) to TOUD is partitioned away so that itmay only be accessed by the processor interface and only then when the SMM bit is set in therequest packet. Non-SMM accesses to this memory region are sent to HI when the TSEG memoryblock is enabled.00 =Reserved01 =Reserved10=(TOUD + 512 KB) to TOUD11 =(TOUD + 1 MB) to TOUDTSEG Enable (T_EN)—R/W/L. This bit enables SMRAM memory for Extended SMRAM spaceonly. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriatephysical address space. Note that once D_LCK is set, this bit becomes read only.Intel ® 82865G/82865GV GMCH Datasheet 73