Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.10.4 DRC—DRAM Controller Mode Register (Device 6, MMR)Address Offset:Default Value:Access:Size:0068h–006Bh00000001hR/W, RO32 bitsBitDescription31:30 Reserved.29Initialization Complete (IC)—R/W. This bit is used for communication of the software statebetween the memory controller and the BIOS.1 = BIOS sets this bit to 1 after initialization of the DRAM memory array is complete.28:23 Reserved.Number of Channels (CHAN)—R/W. The GMCH memory controller supports three modes ofoperation. When programmed for single-channel mode, there are three options: channel A ispopulated, channel B is populated, or both are populated but not identically. When both channelshave DIMMs installed and they are not identical (from channel to channel), the controller operatesin a mode that is referred to as virtual single-channel. In this mode, the two physical channels arenot in lock step but act as one logical channel. To operate in either dual-channel mode, the two22:21 channels must be populated identically.00 = Single-channel or virtual single-channel01 = Dual-channel, linear organization10 = Dual-channel, tiled organization11 = Reserved20:11 ReservedRefresh Mode Select (RMS)—R/W. This field determines whether refresh is enabled and, if so, atwhat rate refreshes will be executed.000 = Reserved001 = Refresh enabled. Refresh interval 15.6 µsec10:8010 = Refresh enabled. Refresh interval 7.8 µsec011 = Refresh enabled. Refresh interval 64 µsec111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode)Other = Reserved7 Reserved.136 Intel ® 82865G/82865GV GMCH Datasheet