IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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Register Description3.6.1 VID1—Vendor Identification Register (Device 1)Address Offset: 00–01hDefault Value: 8086hAccess:ROSize:16 bitsThe VID register contains the vendor identification number. This 16-bit register, combined with theDevice Identification register, uniquely identify any PCI device.Bit15:0DescriptionsVendor Identification Device 1 (VID1)—RO. This register field contains the PCI standardidentification for Intel, 8086h.3.6.2 DID1—Device Identification Register (Device 1)Address Offset: 02–03hDefault Value: 2571hAccess:ROSize:16 bitsThis 16-bit register, combined with the Vendor Identification register, uniquely identifies any PCIdevice.BitDescriptions15:0 Device Identification Number (DID)—RO. A 16-bit value assigned to the GMCH device 1.88 Intel ® 82865G/82865GV GMCH Datasheet
Register Description3.6.3 PCICMD1—PCI Command Register (Device 1)Address Offset: 04–05hDefault Value: 0000hAccess:RO, R/WSize:16 bitsBitDescriptions15:10 Reserved.9 Fast Back-to-Back Enable (FB2B)—RO. Hardwired to 0.SERR Message Enable (SERRE)—R/W. This bit is a global enable bit for Device 1 SERRmessaging. The GMCH communicates the SERR# condition by sending a SERR message to theICH5.8 0 = Disable. SERR message is not generated by the GMCH for Device 1.1 = Enable. GMCH is enabled to generate SERR messages over HI for specific Device 1 errorconditions that are individually enabled in the BCTRL1 register. The error status is reported inthe PCISTS1 register.7 Address/Data Stepping (ADSTEP)—RO. Hardwired to 0.Parity Error Enable (PERRE)—RO. Hardwired to 0. Parity checking is not supported on the6primary side of this device.5 Reserved.4 Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0.3 Special Cycle Enable (SCE)—RO. Hardwired to 0.210Bus Master Enable (BME)—R/W.0 = Disable. AGP Master initiated Frame# cycles will be ignored by the GMCH. The result is amaster abort. Ignoring incoming cycles on the secondary side of the PCI-to-PCI bridgeeffectively disabled the bus master on the primary side. (default)1 = Enable. AGP master initiated Frame# cycles will be accepted by the GMCH if they hit a validaddress decode range. This bit has no affect on AGP Master originated SBA or PIPE# cycles.Memory Access Enable (MAE)—R/W.0 = Disable. All of Device 1’s memory space is disabled.1 = Enable. Enables the memory and pre-fetchable memory address ranges defined in theMBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.IO Access Enable (IOAE)—R/W.0 = Disable. All of Device 1’s I/O space is disabled.1 = Enable. This bit must be set to1 to enable the I/O address range defined in the IOBASE1, andIOLIMIT1 registers.Intel ® 82865G/82865GV GMCH Datasheet 89
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Intel ® 865G/865GV ChipsetDatashee
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Contents1 Introduction.............
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3.8 PCI-to-CSA Bridge Registers (De
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5.5.3 Synchronous Display .........
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Tables1 General Terminology .......
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Introduction1.4 Intel ® 82865G GMC
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Introduction1.4.7 Display Interface
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Signal Description2.1 Host Interfac
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Signal DescriptionSignal Name Type
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Signal Description2.2.2 DDR SDRAM C
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Signal Description2.5 AGP Interface
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Signal Description2.5.4 AGP Strobes
Page 37 and 38: Signal DescriptionSignal Name Type
Page 39 and 40: Signal Description2.5.7 Intel ® DV
Page 41 and 42: Signal Description2.7 Clocks, Reset
Page 44 and 45: Signal Description2.10 GMCH Sequenc
Page 46 and 47: Signal Description2.12 Full and War
Page 48 and 49: Register DescriptionTermReservedReg
Page 50 and 51: Register Description3.3 Routing Con
Page 52 and 53: Register DescriptionIf the Bus Numb
Page 54 and 55: Register Description3.4.2 CONFIG_DA
Page 56 and 57: Register DescriptionTable 6.DRAM Co
Page 58 and 59: Register Description3.5.3 PCICMD—
Page 60 and 61: Register Description3.5.5 RID—Rev
Page 62 and 63: Register Description3.5.10 APBASE
Page 64 and 65: Register Description3.5.14 AGPM—A
Page 66 and 67: Register DescriptionNotes on Pre-Al
Page 68 and 69: Register Description3.5.17 FPLLCONT
Page 70 and 71: Register DescriptionAs an example,
Page 72 and 73: Register Description3.5.20 SMRAM—
Page 74 and 75: Register Description3.5.22 ACAPID
Page 76 and 77: Register Description3.5.24 AGPCMD
Page 78 and 79: Register Description3.5.26 APSIZE
Page 80 and 81: Register Description3.5.29 LPTT—A
Page 82 and 83: Register Description3.5.31 GMCHCFG
Page 84 and 85: Register Description3.5.32 ERRSTS
Page 86 and 87: Register Description3.5.34 SKPD—S
Page 90 and 91: Register Description3.6.4 PCISTS1
Page 92 and 93: Register Description3.6.8 MLT1—Ma
Page 94 and 95: Register Description3.6.14 IOBASE1
Page 96 and 97: Register Description3.6.17 MBASE1
Page 100: Register Description3.6.22 ERRCMD1
Page 105 and 106: Register Description3.7.6 CC—Clas
Page 107 and 108: Register Description3.7.11 MMADR—
Page 109 and 110: Register Description3.7.16 CAPPOINT
Page 111 and 112: Register Description3.7.22 PMCAP—
Page 113 and 114: Register Description3.8 PCI-to-CSA
Page 115 and 116: Register Description3.8.3 PCICMD3
Page 117 and 118: Register Description3.8.5 RID3—Re
Page 119 and 120: Register Description3.8.11 SBUSN3
Page 121 and 122: Register Description3.8.15 SSTS3—
Page 123 and 124: Register Description3.8.17 MLIMIT3
Page 125 and 126: Register Description3.8.20 BCTRL3
Page 127 and 128: Register Description3.9 Overflow Co
Page 129 and 130: Register Description3.9.4 PCISTS6
Page 131 and 132: Register Description3.9.9 BAR6—Me
Page 133 and 134: Register DescriptionThe remaining 7
Page 135 and 136: Register Description3.10.3 DRT—DR
Page 137 and 138: Register DescriptionBit6:4Descripti
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System Address MapSystem Address Ma
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System Address Map4.2 Compatibility
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System Address Map4.3 Extended Memo
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System Address MapPCI Memory Addres
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Functional DescriptionFunctional De
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Functional Description5.2 System Me
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Functional Description5.2.2.1 Dynam
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Functional DescriptionTable 21. DRA
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Functional DescriptionTable 23. DRA
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Functional Description5.2.6 Configu
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Functional Description5.3.1 GMCH AG
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Functional Descriptiondown controll
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Functional Description5.3.6 Support
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Functional Description5.4.1 3D Engi
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Functional DescriptionTexture Forma
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Functional DescriptionTexture Map B
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Functional DescriptionDepth BufferT
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Functional Description5.4.3 Video E
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Functional Description5.4.5 PipesSc
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Functional DescriptionIntegrated RA
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Functional DescriptionDirect YUV fr
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Functional Description• System—
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Functional Description5.8 ClockingT
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Electrical CharacteristicsElectrica
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Electrical CharacteristicsTable 36.
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Electrical Characteristics6.5 DC Pa
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Electrical Characteristics6.6.3 DAC
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Ballout and Package InformationBall
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Ballout and Package InformationFigu
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Ballout and Package InformationTabl
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Ballout and Package Information7.2
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TestabilityTestability 8In the GMCH
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Testability8.2 XOR Chain Definition
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TestabilityTable 45. XOR Chain 1 (3
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Intel ® 82865GV GMCHIntel ® 82865
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Intel ® 82865GV GMCH9.3 Intel ® 8
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Intel ® 82865GV GMCHGMCHCFG—GMCH
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Intel ® 82865GV GMCH BalloutIntel
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Intel ® 82865GV GMCH BalloutFigure
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Intel ® 82865GV GMCH BalloutTable
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Intel ® 82865GV GMCH TestabilityIn
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Intel ® 82865GV GMCH Testability11
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Intel ® 82865GV GMCH TestabilityTa
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IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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