Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.8.8 MLT3—Master Latency Timer Register (Device 3)Address Offset:Default Value:Access:Size:0Dh00hRO, RW8 bitsThis functionality is not applicable. It is described here since these bits should be implemented as aread/write to prevent standard PCI-to-PCI bridge configuration software from getting “confused.”BitDescription7:3Scratchpad MLT (NA7:3)—R/W. These bits return the value that was last written; however, theyhave no internal function and are implemented as a Scratchpad to avoid confusing software.2:0 Reserved.3.8.9 HDR3—Header Type Register (Device 3)Address Offset:Default Value:Access:Size:0Eh01hRO8 bitsThis register identifies the header layout of the configuration space.Bit7:0DescriptionHeader Type Register (HDR)—RO.01h = GMCH Device 3 is a single function device with bridge header layout.3.8.10 PBUSN3—Primary Bus Number Register (Device 3)Address Offset:Default Value:Access:Size:18h00hRO8 bitsThis register identifies that virtual PCI-to-PCI bridge is connected to bus 0.Bit7:0DescriptionPrimary Bus Number (BUSN)—RO. Configuration software typcially programs this field with thenumber of the bus on the primary side of the bridge. Since Device 3 is an internal device and itsprimary bus is always 0, these bits are read only and are hardwired to 00h.118 Intel ® 82865G/82865GV GMCH Datasheet