Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.5 DRAM Controller/Host-Hub Interface DeviceRegisters (Device 0)This section contains the DRAM Controller and Host-Hub Interface PCI configuration registerslisted in order of ascending offset address. The register address map is shown in Table 6.Table 6.DRAM Controller/Host-Hub Interface Device RegisterAddress Map (Device 0) (Sheet 1 of 2)AddressOffsetRegisterSymbolRegister Name Default Value Access00–01h VID Vendor Identification 8086h RO02–03h DID Device Identification 2570h RO04–05h PCICMD PCI Command 0006h RO, R/W06–07h PCISTS PCI Status 0090h RO, R/WC08h RID Revision IdentificationSee registerdescriptionRO09h — Intel Reserved — —0Ah SUBC Sub-Class Code 00h RO0Bh BCC Base Class Code 06h RO0C — Intel Reserved — —0Dh MLT Master Latency Timer 00h RO0Eh HDR Header Type 00h RO0Fh — Intel Reserved — —10–13h APBASE Aperture Base Configuration 00000008h RO, R/W14–2Bh — Intel Reserved — —2C–2Dh SVID Subsystem Vendor Identification 0000h R/WO2E–2Fh SID Subsystem Identification 0000h R/WO30–33h — Intel Reserved — —34h CAPPTR Capabilities Pointer E4h RO35–50h — Intel Reserved — RO51h AGPM AGP Miscellaneous Configuration 00h R/W52h GC Graphics Control 0000_1000b R/W53h CSABCONT CSA Basic Control 00h RO, R/W54-5Fh — Intel Reserved — —60h FPLLCONT FPLL Clock Control 00h R/W, RO61–89h — Intel Reserved — —90h PAM0 Programmable Attribute Map 0 00h RO, R/W91h PAM1 Programmable Attribute Map 1 00h RO, R/W92h PAM2 Programmable Attribute Map 2 00h RO, R/W93h PAM3 Programmable Attribute Map 3 00h RO, R/W94h PAM4 Programmable Attribute Map 4 00h RO, R/WIntel ® 82865G/82865GV GMCH Datasheet 55